Control circuit and method for programming an output voltage of a power converter

#The present invention is related generally to programmable power converters. More particularly, the present invention is related to a control circuit and method for programming an output voltage of a power converter.

#One of the charging methods for the portable electronic devices, for example the smart phones and the tablet personal computers, is to utilize a power converter to convert the power into the output voltage. The output voltage is provided to the electronic devices for charging through the transmission line connected to the power converter. FIG. 1 shows a conventional power converter 2, which includes a transformer TX generated an output voltage VOUT at a secondary side of the transformer TX. Resistors R1 and R2 form a voltage divider which is coupled to an output terminal of the power converter 2 to detect the output voltage VOUT and to divide the output voltage VOUT to generate a voltage signal VDIV. A shunt regulator 4 is coupled to the resistors R1 and R2 as well as an optical coupler 6. The shunt regulator 4 will compare the voltage signal VDIV with a reference voltage to determine the current Is flowing through the optical coupler 6. Accordingly, the optical coupler 6 generates a feedback signal Ifb related to the current Is for a control integrated circuit (not shown in FIG. 1) to regulate the output voltage VOUT. There are more and more systems that need to change the output voltage VOUT according to different needs, for example the rapid charging mode or the sleep mode, in order to improve their performance. There are two existing methods for changing the feedback signal Ifb in order to change the output voltage VOUT: changing a divider ratio of the voltage divider to adjust the voltage signal VDIV, or choosing a different reference voltage.

#As disclosed by U.S. Pat. No. 5,773,963, one of the methods for changing a divider ratio to adjust the output voltage of a power converter is illustrated in FIG. 2, in which a power circuit 8 converts a power input VAC into an output voltage VOUT for charging a battery 10. The output voltage VOUT is divided by a divider ratio to generate a voltage signal VDIV that is compared with a reference voltage Vref to generate a feedback signal SFB for the power circuit 8 to adjust the output voltage VOUT. A microcontroller 12 controls the switching of a transistor Q1 so as to determine whether a resistor R3 and the resistor R2 should be in a parallel connection. Accordingly, the divider ratio will be controlled and thereby adjust the output voltage VOUT.

#These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments according to the present invention taken in conjunction with the accompanying drawings, in which:

#FIG. 1 shows a conventional power converter;

#FIG. 2 shows a conventional method for changing a divider ratio of a voltage divider;

#FIG. 4 shows a first embodiment of the present invention, and FIG. 5 shows a simplified circuitry of FIG. 4. Referring to FIGS. 4 and 5, at a secondary side of a transformer TX of a power converter 2, an optical coupler 6 is served as a feedback loop for providing a feedback signal Ifb related to the output voltage VOUT to regulate the output voltage VOUT. A control circuit 16 is coupled to the optical coupler 6 for controlling the feedback signal Ifb so as to regulate the output voltage VOUT. Alternatively, the optical coupler 6 can be replaced by other feedback loop.

#The control circuit 16 includes a voltage divider 18 that is formed by the series resistors R1 and R2 for dividing the output voltage VOUT to generate a voltage signal VDIV for controlling the feedback signal Ifb. An offset current generator 20 has a terminal 22 coupled to the voltage divider 18 and a terminal 24 coupled to a microcontroller 26. The offset current generator 20 injects a current I1 to the voltage divider 18 or sinks a current I2 from the voltage divider 18, thereby adjusting the voltage signal VDIV so as to adjust the output voltage VOUT. In the offset current generator 20, a decoder 28 decodes a digital signal SD1 to generate control signals SC1 and SC2 as well as switch signals SS1 and SS2. A digital to analog converter 30 is coupled to the decoder 28 and the voltage divider 18. The digital to analog converter (DAC) 30 includes switches SW1 and SW2 and variable current sources 32 and 34. The switch SW1 is coupled between the variable current source 32 and the voltage divider 18. The switch SW2 is coupled between the voltage divider 18 and the variable current source 34. The variable current source 32 adjusts the amount of the current I1 according to the control signal SC1, and the variable current source 34 adjusts the amount of the current I2 according to the control signal SC2. The switches SW1 and SW2 will be turned on or turned off according to the switch signals SS1 and SS2. When the switch signal SS1 turns on the switch SW1, the variable current source 32 injects the current I1 into the resistor R2 in the voltage divider 18. When the switch signal SS2 turns on the switch SW2, the variable current source 34 sinks the current I2 from the resistor R2 in the voltage divider 18.

#The control circuit 16 shown in FIG. 4 further includes a microcontroller 26 that includes a program memory 46 and a data memory 48 for saving information. The microcontroller 26 generates the digital signals SD1 and SD2 according to the saved information to the decoder 28 and a digital to analog converter 36, respectively. According to the digital signal SD2, the digital to analog converter 36 generates a reference voltage Vref at an output terminal 38 and generates an overvoltage threshold Vref_ov at an output terminal 40. An error amplifier 42 has a positive input terminal coupled to the voltage divider 18 and the digital to analog converter 30, a negative input terminal coupled to the output terminal 38 of the digital to analog converter 36, and an output terminal connected to a control terminal 50 of a transistor Q8. The transistor Q8 is coupled between the optical coupler 6 and a ground terminal. The error amplifier 42 controls the current Is flowing through the transistor Q8 according to a difference between the voltage signal VDIV and the reference voltage Vref. The optical coupler 6 generates the feedback signal Ifb according to the current Is. A shunt regulator 4 in FIG. 5 is formed by the transistor Q8 and the error amplifier 42. In this embodiment, a comparator 44 is utilized for achieving an overvoltage protection, in which a positive input terminal of the comparator 44 is coupled to the voltage divider 18, and a negative input terminal of the comparator 44 is coupled to the output terminal 40 of the digital to analog converter 36. When the voltage signal VDIV is higher than the overvoltage threshold Vref_ov, the comparator 44 generates a protecting signal Sov to turn off the power converter 2 so as to achieve the overvoltage protection. In other embodiments, the comparator 44 can be also utilized for achieving an under voltage protection. In such circumstances, the digital to analog converter 36 will provide an under voltage threshold supplied to the positive terminal of the comparator 44, and the negative input terminal of the comparator 44 will receive the voltage signal VDIV. When the voltage signal VDIV is lower than the under voltage threshold, the comparator 44 will generate a protecting signal to turn off the power converter 2, thereby achieving the under voltage protection.