US 10,097,027 B2Granted

Light load detection and current drain cutoff in a power bank device

AssigneeActive-Semi, Inc.

InventorHong Mao

Life of this patent

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Abstract

A power bank device has an input connector, an output connector, a DC-to-DC switching converter, a plurality of battery cells coupled together in series, and novel light load detection circuitry. The power bank device is operable in a discharging mode in which the battery cells power the DC-to-DC converter, and the converter drives a regulated DC voltage onto the output connector. The detection circuitry detects whether a light load condition exists in which only a small amount of current is being output onto the output connector. If the condition is detected, then the converter is disabled so that current flow out of the output connector is stopped. In one example, the condition is detected by supplying a constant current onto the output connector and detecting whether the voltage on the output connector rises and stays above a predetermined voltage for a predetermined amount of time.

Claims23

Dependent claims

An integrated circuit comprising:

a ground (GND) node;
a voltage input (VIN) node;
a voltage output (VOUT) node;
a battery voltage (VBAT) node;
a DC-to-DC converter control circuit that is operable as part of a DC-to-DC converter, wherein the DC-to-DC converter has a disabled mode, a charging mode and a discharging mode, wherein in the charging mode the DC-to-DC converter receives power via the VIN node and supplies a regulated charging current out of the VBAT node, wherein in the discharging mode the DC-to-DC converter receives power from the VBAT node and drives a regulated DC voltage V1 onto the VOUT node, and wherein in the disabled mode the DC-to-DC converter is disabled so as not to drive any regulated DC voltage onto the VOUT node, wherein the DC-to-DC converter operates in the disabled mode if a first disable signal DIS1 is asserted whereas the DC-to-DC converter can operate in one of the charging mode and the discharging mode if the first disable signal DIS1 is not asserted, and wherein the DC-to-DC converter control circuit outputs a second disable signal DIS2;
a current source coupled to supply a constant current onto the VOUT node, wherein if the second disable signal DIS2 has a first digital logic value then the current source is disabled so that the current source cannot source any current onto the VOUT node whereas if the second disable signal DIS2 has a second digital logic value then the current source is enabled so that the current source can source the constant current onto the VOUT node;
a voltage clamp coupled to the VOUT node;
and
a Voltage Detector and Disable Signal Generating Circuit (VDDSGC) operable to detect a condition in which the voltage on the VOUT node exceeds a second voltage V2 for a predetermined amount of time TD without ever dropping below the second voltage V2 during the predetermined amount of time TD, and in response to detection of the condition the VDDSGC is operable to assert the first disable signal DIS1 so as to prevent the DC-to-DC converter control circuit from sourcing a current onto the VOUT node.

6 more elements

An integrated circuit comprising:

a ground (GND) node;
a voltage input (VIN) node;
a voltage output (VOUT) node;
a battery voltage (VBAT) node;
a DC-to-DC converter control circuit that is operable as part of a DC-to-DC converter, wherein the DC-to-DC converter has a disabled mode, a charging mode and a discharging mode, wherein in the charging mode the DC-to-DC converter receives power via the VIN node and supplies a regulated charging current out of the VBAT node, wherein in the discharging mode the DC-to-DC converter receives power from the VBAT node and drives a regulated DC voltage V1 onto the VOUT node, and wherein in the disabled mode the DC-to-DC converter is disabled so it does not drive any regulated DC voltage onto the VOUT node, wherein the DC-to-DC converter operates in the disabled mode if a first disable signal DIS1 is asserted whereas the DC-to-DC converter can operate in one of the charging mode and the discharging mode if the first disable signal DIS1 is not asserted, and wherein the DC-to-DC converter control circuit outputs a second disable signal DIS2;
and
a light load detection circuit operative to detect a light load condition on the VOUT node, wherein the light load detection circuit is operative to assert the first disable signal DIS1 when it detects the light load condition, wherein the light load detection circuit is operative to receive the second disable signal DIS2, and wherein the light load detection circuit is disabled if the second disable signal DIS2 has a predetermined digital logic value.

4 more elements

An integrated circuit comprising:

a ground (GND) terminal;
a voltage input (VIN) terminal;
a voltage output (VOUT) terminal;
a battery voltage (VBAT) terminal;
a DC-to-DC converter control circuit that is operable as part of a DC-to-DC converter, wherein the DC-to-DC converter has a disabled mode, a charging mode and a discharging mode, wherein in the charging mode the DC-to-DC converter receives power via the VIN terminal and supplies a regulated charging current out of the VBAT terminal, wherein in the discharging mode the DC-to-DC converter receives power from the VBAT terminal and drives a regulated DC voltage V1 onto the VOUT terminal, and wherein in the disabled mode the DC-to-DC converter is disabled so as not to drive any regulated DC voltage onto the VOUT terminal, wherein the DC-to-DC converter operates in the disabled mode if a first disable signal DIS1 is asserted whereas the DC-to-DC converter can operate in one of the charging mode and the discharging mode if the first disable signal DIS1 is not asserted, and wherein the DC-to-DC converter control circuit outputs a second disable signal DIS2;
and
means for detecting a light load condition on the VOUT terminal, wherein the means is also for asserting the first disable signal DIS1 when the means detects the light load condition, and wherein the means is disabled if the second disable signal DIS2 has a predetermined digital logic value.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/602,063Filed 22 May 2017 · continuation
Priority: 13 Mar 2015
Published: US 2017/0256976 A17 Sep 2017
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H02J 7/02
Circuit arrangements for charging or discharging batteries or for supplying loads from batteries: for charging batteries from AC mains by converters
H02J 2207/20
Details of circuit arrangements for charging or discharging batteries or supplying loads from batteries: charging or discharging characterised by…
H02M 1/0032
Details of control, feedback or regulation circuits: control circuits allowing low power mode operation, e.g. in standby mode
Y02B 70/10
Technologies for an efficient end-user side electric power management and consumption: technologies improving the efficiency by using…

Family

Application14/657,222Parent of this continuation · filed 13 Mar 2015
US 2017/0256976 A1Pre-grant publication · published 7 Sep 2017
US 9,692,246 B2Parent of this continuation
US 2016/0268828 A1Published application
US 10,097,027 B2This patent

From the US filing history. Foreign family members aren’t listed.