Reducing undesirable capacitive coupling in transistor devices

A device comprising:

• a first conductor pattern comprising conductive regions and non-conductive regions, and defining at least source and drain conductors of one or more transistors each comprising a semiconductor channel;
• and
• a second conductor pattern over the first conductor pattern and defining at least one or more gate conductors capacitively coupled to the one or more semiconductor channels via a gate dielectric,
• wherein there is overlap between the first and second conductor patterns in some regions,
• wherein the conductive regions of the first conductor pattern comprise addressing line portions and other portions of smaller width than the addressing line portions, and
• wherein the device further comprises a patterned insulator including portions interposed between said second conductor pattern and at least part of said addressing line portions, without any portion of said patterned insulator interposed between said second conductor pattern and said other portions of said first conductor pattern, or between said semiconductor channels and said second conductor pattern, or anywhere over said non-conductive regions;
• and wherein said patterned insulator is interposed between said first conductor pattern and a semiconductor layer providing said one or more semiconductor channels.

A method, comprising:

• depositing a conductor layer on a substrate;
• depositing an insulator layer over the first conductor layer;
• patterning the insulator layer to define a mask for patterning the first conductor layer;
• patterning the first conductor layer using said mask to form a first conductor pattern defining at least source and drain conductors for one or more transistors,
• wherein the first conductor pattern defines first portions having a greater width than other, second portions thereof;
• retaining the patterned insulating layer on at least part of said first portions of said first conductor pattern without retaining said patterned insulating layer on any part of said second portions of the first conductor pattern;
• forming a semiconductor layer over the substrate to form one or more semiconductor channels of the one or more transistors;
• forming a gate dielectric over the semiconductor layer and the patterned insulating layer;
• and
• forming a second conductor pattern over the gate dielectric defining one or more gate conductors for capacitive coupling with the one or more semiconductor channels.