Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
AssigneeSony Semiconductor Solutions Corporation
InventorJun Okuno
Life of this patent
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Abstract
Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
Claims8
A method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes, the method comprising:
- depositing a poly-silicon layer on a substrate;
- depositing a carbon layer above the poly-silicon layer;
- patterning a photo-resist layer on the carbon layer;
- depositing a first spacer layer on the photo-resist layer;
- performing a modified photolithography process on the photo resist layer after etching back the spacer layer, creating sidewalls;
- etching the sidewalls by using the sidewalls as a mask to create a carbon pattern;
- depositing a second spacer layer on the carbon pattern;
- etching back the second spacer layer;
- exhuming the carbon pattern leaving pairs of carbon sidewalls;
- performing an etching process to form trenches;
- stripping all layers except the poly-silicon layer and the substrate, forming stacks topped with poly-silicon;
- implanting a bottom electrode in each of the trenches;
- and
- implanting a top electrode in each of the stacks.
A method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes, the method comprising:
- depositing a poly-silicon layer on a substrate;
- depositing a carbon layer above the poly-silicon layer;
- patterning a photo-resist layer on the carbon layer;
- depositing a first spacer layer on the photo-resist layer, wherein after the photo-resist layer is patterned, the photo-resist layer is shrunk to achieve a greater wordline width, wherein shrinking is performed using a dry etching process, and wherein shrinking is performed using a heating process.
A memory device comprising:
- a plurality of memory cells coupled to a plurality of wordlines,
- wherein a bottom electrode of a transistor coupled to each of the plurality of memory cells is spaced a predetermined distance away from a bottom electrode of a transistor coupled to a neighboring memory cell to prevent thermal disturbances among neighboring memory cells, and
- wherein a ratio of the width of the bottom electrode to the width of the distance between neighboring electrodes is 1.2 or greater.
Dependencies are inferred from the claim text.