Semiconductor chip having tampering feature

A method of fabricating a semiconductor chip having a tampering feature, comprising:

• obtaining a structure including a first semiconductor layer and an electrically insulating layer adjoining the first semiconductor layer;
• forming electronic circuitry on the first semiconductor layer during a front-end-of-line fabrication process;
• depositing a dielectric layer encasing the electronic circuitry;
• forming a second semiconductor layer on the dielectric layer;
• forming a triggering circuit including a normally-OFF heterojunction field-effect photo-transistor during a back-end-of-line fabrication process at a temperature of less than 400° C., the normally-OFF heterojunction field-effect transistor being formed on the second semiconductor layer and being positioned above the electronic circuitry;
• providing an actuating element on the dielectric layer;
• electrically connecting the actuating element to the normally-OFF heterojunction field-effect transistor;
• forming a reactive layer on the dielectric layer for disabling the electronic circuitry, the reactive layer being reactive to current flowing through the normally-OFF heterojunction field-effect photo-transistor and the actuating element, and
• forming an encapsulation layer encapsulating the reactive layer.