US 10,096,720 B2Granted

Transistor, semiconductor device, and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorYoshinori Ando

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Abstract

To provide a semiconductor device with high design flexibility. A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. A semiconductor layer where a channel of the first transistor is formed and a semiconductor layer where a channel of the second transistor is formed are formed using semiconductor materials having different electron affinities. When an oxide semiconductor is used for the semiconductor layer, an insulating layer containing excess oxygen is used as an insulating layer below the semiconductor layer. By increasing the thickness of the insulating layer, a large amount of oxygen can be supplied to the semiconductor layer.

Claims19

Dependent claims

A transistor comprising:

a wiring;
a first electrode comprising a region overlapping with the wiring;
a second electrode;
a third electrode;
a fourth electrode;
a first semiconductor layer;
a second semiconductor layer comprising a region overlapping with the first semiconductor layer, the second semiconductor layer comprising a first region, a second region, and a third region, wherein the third region is sandwiched between the first region and the second region;
a third semiconductor layer;
a first layer comprising a region overlapping with the second electrode in the region overlapping with the first region;
a second layer comprising a region overlapping with the third electrode in the region overlapping with the second region;
a first insulating layer comprising a region overlapping with the wiring;
a second insulating layer comprising a region overlapping with the first electrode and a region overlapping with the first insulating layer;
and
a third insulating layer,
wherein the first semiconductor layer comprises a region overlapping with the second insulating layer,
wherein the second electrode comprises a region overlapping with the first region,
wherein the third electrode comprises a region overlapping with the second region,
wherein the third semiconductor layer comprises a region overlapping with the first layer, a region overlapping with the second layer, and a region overlapping with the third region, and
wherein the fourth electrode comprises a region overlapping with the third region with the third insulating layer located between the fourth electrode and the third region.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/464,517Filed 21 Mar 2017
Priority: JP 2016-06186925 Mar 2016
Published: US 2017/0278973 A128 Sep 2017
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 30/6734
Multi-gate TFTs: having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
H10D 86/0221
Of multiple TFTs: comprising manufacture, treatment or patterning of TFT semiconductor bodies