Thin film transistor array panel and method of manufacturing the same

A method for manufacturing a thin film transistor array panel, the method comprising:

• forming a data line on a substrate;
• forming a buffer material layer on the substrate and the data line;
• forming a first oxide semiconductor pattern on the buffer material layer;
• forming a gate insulating pattern and a gate electrode on the first oxide semiconductor pattern;
• and
• forming a buffer layer by etching a portion of the buffer material layer that is, in a plan view, spaced apart from the gate insulating pattern and the gate electrode,
• wherein the first oxide semiconductor pattern overlaps a portion of the buffer layer in a direction of the plan view.

A thin film transistor array panel comprising:

• a substrate;
• a data line disposed on a first area of the substrate;
• a buffer layer disposed on a second area of the substrate, the second area being spaced apart from the first area;
• a thin film transistor disposed on the buffer layer, the thin film transistor comprising an oxide semiconductor layer;
• and
• a pixel electrode connected to the thin film transistor,
• wherein the buffer layer comprises:
• a first region overlapping the oxide semiconductor layer;
• and
• a second region extending from the first region, the second region being less thick than the first region.

A method of manufacturing a thin film transistor array panel comprising:

• forming a data line on a substrate;
• forming a buffer material layer on the substrate and the data line;
• forming a first oxide semiconductor pattern on the buffer material layer;
• forming a gate insulating pattern and a gate electrode on the first oxide semiconductor pattern;
• forming a second oxide semiconductor pattern from the first oxide semiconductor pattern, formation of the second oxide semiconductor pattern forming a buffer material layer pattern from the buffer material layer;
• and
• forming a buffer layer from the buffer material layer pattern,
• wherein the buffer layer comprises:
• a first portion overlapping the second oxide semiconductor pattern;
• and
• a second portion extending from the first portion, the second portion being less thick than the first portion.

A thin film transistor array panel comprising:

• a substrate;
• a data line disposed on the substrate;
• a buffer layer disposed on the substrate and spaced apart from the data line in a plan view;
• a thin film transistor disposed on the buffer layer, the thin film transistor comprising an oxide semiconductor layer;
• a pixel electrode connected to the thin film transistor;
• and
• a light blocking layer disposed on a same layer as the data line, the light blocking layer overlapping the thin film transistor,
• wherein the buffer layer overlaps the light blocking layer, and
• wherein:
• the buffer layer comprises a first region and a second region;
• thicknesses of the first and second regions are different;
• and
• the second region overlaps an edge of the light blocking layer.