Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

A semiconductor device, comprising:

• a substrate having a surface;
• a first source/drain region disposed on the surface of the substrate;
• a vertical channel region disposed on the first source/drain region;
• a plurality of lattice defects confined to the first source/drain region, wherein the vertical channel region is essentially defect-free;
• a second source/drain region disposed on the vertical channel region, wherein the second source/drain region has an upper lateral portion and a lower vertical portion, the lower vertical portion on the vertical channel region, and the lower vertical portion having first and second sides, wherein the upper lateral portion extends beyond both the first and second sides of the lower vertical portion, and wherein the upper lateral portion has a lateral width greater than a lateral width of the vertical channel region;
• and
• a gate stack disposed on and completely surrounding a portion of the vertical channel region, wherein the gate stack is not in physical contact with the upper lateral portion of the second source/drain region.

A method of fabricating a semiconductor device, the method comprising:

• forming an insulator layer on a surface of a substrate;
• patterning the insulator layer to form an opening in the insulator layer, the opening exposing a portion of the surface of the substrate;
• forming a first source/drain region in the opening, on the surface of the substrate;
• forming a vertical channel region in the opening, on the first source/drain region;
• forming a second source/drain region in the opening, on the vertical channel region, wherein the second source/drain region has an upper lateral portion and a lower vertical portion, the lower vertical portion on the vertical channel region, and the lower vertical portion having first and second sides, wherein the upper lateral portion extends beyond both the first and second sides of the lower vertical portion, and wherein the upper lateral portion has a lateral width greater than a lateral width of the vertical channel region;
• recessing the insulator layer to expose a portion of the vertical channel region;
• and
• forming a gate stack on and completely surrounding an exposed portion of the vertical channel region, wherein the gate stack is not in physical contact with the upper lateral portion of the second source/drain region.