Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same
AssigneeMagnaChip Semiconductor, Ltd.
InventorsYoung Bae Kim, Kwang Il Kim
Life of this patent
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Abstract
The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.
Claims18
A method for forming a semiconductor device, the method comprising:
- providing a substrate;
- forming a first deep well region of a first conductivity type in a first portion of the substrate;
- forming a second deep well region of the first conductivity type in a second portion of the substrate, the first and second deep well regions being formed with an identical doping concentration and doping depth;
- forming a deep diffusion region of the first conductivity type in the substrate between the first deep well region and the second deep well region;
- forming a third well region of a second conductivity type in the deep diffusion region, the third well region being a gate region of a junction field effect transistor (JFET) and configured to control a pinch off voltage of the JFET;
- forming an insulation layer on a top surface of the substrate;
- forming a buried impurity layer of the second conductivity type in the first and second deep well regions, the buried impurity layer being in electrical contact with the third well region;
- forming a drain region in the first portion of the substrate;
- and
- forming a source region in the second portion of the substrate, the source region and the drain region being of the first conductivity type.
A method for forming a semiconductor device, the method comprising:
- providing a substrate;
- forming a deep well region of a first conductivity type in the substrate, wherein the deep well region comprises a first deep well region of the first conductivity type in a first portion of the substrate, and a second deep well region of the first conductivity type in a second portion of the substrate;
- forming a deep diffusion region of the first conductivity type in the substrate between the first deep well region and the second deep well region, the deep diffusion region having a doping concentration that is lower than that of the first and second well regions;
- forming an insulation layer on a top surface of the substrate;
- forming a buried impurity layer of the second conductivity type in the first and second deep well regions;
- forming a drain region in the first deep well region;
- and
- forming a source region in the second deep well region, the source region and the drain region being of the first conductivity type.
A method for forming a semiconductor device, the method comprising:
- forming a deep well region of a first conductivity type on a substrate, the deep well region comprising a diffusion region having a dopant concentration lower than that of the deep well region;
- forming a junction field effect transistor (JFET) gate region of a second conductivity type on a portion of the diffusion region, the JFET gate region being configured to control a pinch-off voltage of the JFET;
- forming a buried impurity layer of the second conductivity type in the deep well region, the buried impurity layer being in electrical contact with the JFET gate region;
- forming a common drain region and a first source region of the first conductivity type on the deep well region;
- and
- forming a second source region of the first conductivity type on a body region of the second conductivity type formed on the substrate.
Dependencies are inferred from the claim text.