Vertical device architecture

A vertical transistor device, comprising:

• a source region over a substrate;
• a channel region over the source region, wherein the channel region has a bottom surface with an elongated shape;
• a conductive gate region separated from sidewalls of the channel region by a gate dielectric layer, wherein the conductive gate region comprises a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg;
• a drain contact over the channel region;
• a drain spacer over the conductive gate region and below a lower surface of the drain contact, wherein the drain spacer laterally surrounds the channel region and the drain contact;
• and
• an inter-level dielectric (ILD) layer laterally separated from the channel region and the drain contact by the drain spacer.

A vertical transistor device, comprising:

• a source structure over a substrate;
• a channel structure over the source structure, wherein the channel structure has a bottom surface with an elongated shape;
• a conductive gate structure overlying the source structure at a position separated from sidewalls of the channel structure by a gate dielectric layer, wherein the conductive gate structure comprises a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg, and wherein the gate dielectric layer separates the conductive gate structure from a plane extending along a topmost surface of the source structure;
• and
• a drain contact over the channel structure.