Multi-step surface passivation structures and methods for fabricating same
AssigneeEfficient Power Conversion Corporation
InventorsRobert Beach, Robert Strittmatter, Chunhua Zhou, Guangyuan Zhao, Jianjun Cao
Life of this patent
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Abstract
A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Qgd). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.
Claims24
A column III nitride transistor comprising:
- a substrate;
- a transition layer positioned above the substrate, wherein the transition layer comprises a column III nitride material;
- a buffer layer positioned above the transition layer, wherein the buffer layer comprises a column III nitride material;
- a barrier layer positioned immediately above the buffer layer, wherein the barrier layer comprises a column III nitride material;
- a channel comprising a conductive two-dimensional electron gas (2DEG) formed in the buffer layer at the junction with the barrier layer;
- gate, drain, and source contacts positioned above the barrier layer, wherein the gate contact is positioned between the source and drain contacts;
- and
- a first insulator and a second insulator positioned above the barrier layer and at least between the gate and drain contacts, wherein the first insulator is nearer to the gate contact than the second insulator, and wherein at least a part of the first insulator is positioned lateral to at least a part of the second insulator;
- wherein net electron donor density above the channel under the first insulator is lower than net electron donor density above the channel under the second insulator, such that 2DEG density in the channel under the second insulator is higher than 2DEG density in the channel under the first insulator.
A column III nitride transistor comprising:
- a substrate;
- a transition layer positioned above the substrate, wherein the transition layer comprises a column III nitride material;
- a buffer layer positioned above the transition layer, wherein the buffer layer comprises a column III nitride material;
- a barrier layer positioned immediately above the buffer layer, wherein the barrier layer comprises a column III nitride material;
- a channel comprising a conductive two-dimensional electron gas (2DEG) formed in the buffer layer at the junction with the barrier layer;
- gate, drain, and source contacts positioned above the barrier layer, wherein the gate contact is positioned between the source and drain contacts;
- a first insulator and a second insulator positioned above the barrier layer and at least between the gate and drain contacts, wherein the first insulator is nearer to the gate contact than the second insulator;
- and
- an insulator offset layer positioned at least between the second insulator and the barrier layer;
- wherein net electron donor density above the channel under the first insulator is lower than net electron donor density above the channel under the second insulator, such that 2DEG density in the channel under the second insulator is higher than 2DEG density in the channel under the first insulator.
Dependencies are inferred from the claim text.