Process for fabricating a vertical-channel nanolayer transistor

A process for fabricating a vertical transistor, comprising steps of:

• providing a substrate surmounted by a stack of first, second, and third layers made of first, second, and third semiconductor materials, respectively, said second semiconductor material being different from the first and third semiconductor materials;
• partially etching the first and third layers with an etching that is selective with respect to the second layer and that is stopped on a lower surface and on an upper surface of the second layer, so as to form a first void in the first layer and a third void in the third layer, said first and third voids extending to the lower surface and to the upper surface of the second layer, respectively;
• filling said first and third voids with a dielectric material in order to form first and second spacers that make contact with the lower surface and the upper surface of the second layer, respectively;
• partially etching the second layer with an etching that is selective with respect to the dielectric material of said first and second spacers, so as to form a second void in the second layer between the first and second spacers;
• and
• depositing a conductor material in the second void.