Vertical field effect transistor with reduced parasitic capacitance
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
Life of this patent
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Abstract
Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.
Claims19
A method for forming a semiconductor device, the method comprising:
- forming a semiconductor fin on a substrate;
- forming a first bottom spacer on a surface of the substrate and a sidewall of the semiconductor fin;
- forming a sacrificial spacer over a channel region of the semiconductor fin and a portion of the first bottom spacer;
- forming a second bottom spacer on a surface of the first bottom spacer and adjacent to the sacrificial spacer;
- removing the sacrificial spacer;
- and
- forming a conductive gate over the channel region of the semiconductor fin;
- wherein the conductive gate is formed such that a first portion of the conductive gate is on the portion of the first bottom spacer and a second portion of the conductive gate is on the second bottom spacer.
A method for forming a semiconductor device, the method comprising:
- forming a semiconductor fin on a substrate;
- forming a first bottom spacer on a surface of the substrate and a sidewall of the semiconductor fin;
- forming a sacrificial spacer over a channel region of the semiconductor fin and a portion of the first bottom spacer;
- forming a second bottom spacer on a surface of the first bottom spacer;
- removing the sacrificial spacer;
- forming a gate material over the channel region and on the first and second bottom spacers;
- planarizing the gate material to a surface of the second bottom spacer;
- recessing the second bottom spacer;
- and
- forming a metal layer over the recessed second bottom spacer.
A semiconductor device, comprising:
- a semiconductor fin formed on a substrate;
- a conductive gate over a channel region of the semiconductor fin;
- and a bottom spacer between the conductive gate and the substrate;
- wherein the bottom spacer comprises a first portion comprising a first thickness and a second portion comprising a second thickness greater than the first thickness;
- wherein the first portion is between the second portion and the semiconductor fin.
Dependencies are inferred from the claim text.