Low end parasitic capacitance FinFET
AssigneeInternational Business Machines Corporation
InventorEffendi Leobandung
Life of this patent
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Abstract
Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a gate structure and depositing an insulating material around the gate structure; selectively etching an active device area; forming a set of spacers on the sides of the gate structure; growing a doped source and drain region; depositing an insulator over an upper surface of a deposited etch stop layer; and depositing a metal into a contact opening to form one or more contacts.
Claims19
A method for fabricating a semiconductor device comprising:
- providing a semiconductor substrate comprising a plurality of fins etched in the semiconductor substrate having a set of gate structures;
- creating device regions in the semiconductor substrate using shallow trench isolation (STI);
- filling the device regions with an insulator;
- planarizing the insulator;
- recessing the insulator, wherein the insulator has a thickness which is less than a height of the plurality of fins;
- depositing a first insulating material between the set of gate structures;
- selectively etching an active device area;
- depositing an oxide material over a top surface of the active device area;
- removing the first insulating material selective to the plurality of fins;
- forming a set of spacers adjacent to the set of gate structures;
- growing a doped source and drain region adjacent to the plurality of fins;
- depositing an etch stop layer over an upper surface of the deposited oxide material;
- depositing a second insulating material over an upper surface of the deposited etch stop layer;
- and
- depositing a metal within a contact opening to form a plurality of contacts.
A semiconductor structure comprising:
- a plurality of fins each having a respective source and drain region patterned in a starting semiconductor substrate;
- a set of gate structures formed on the starting semiconductor substrate;
- a set of spacers formed around each of the set of gate structures;
- an insulating material, wherein the insulating material is configured to be deposited over an upper surface of an active semiconductor device area;
- and
- a plurality of contacts, wherein a bottom surface of the plurality of contacts are positioned above the active semiconductor device area.
Dependencies are inferred from the claim text.