Monolithically integrated resistive memory using integrated-circuit foundry compatible processes

A method of fabricating a memory device, comprising:

• fabricating a pair of metal layers having a defined distance there between;
• and
• fabricating a monolithic stack that comprises multiple layers, wherein the fabricating is performed within a thermal budget of a substrate of the memory device and with a stack height less than or equal to the defined distance, the fabricating comprises:
• providing the substrate comprising one or more complementary metal-oxide semiconductor devices;
• fabricating a first insulator layer over the substrate;
• fabricating a first metal layer of the pair of metal layers over the first insulator layer;
• fabricating an interlayer dielectric material layer over the first metal layer;
• fabricating a resistive memory device structure within the interlayer dielectric material layer comprising forming a pillar device;
• fabricating a second metal layer of the pair of metal layers over the resistive memory device structure;
• and
• forming an electrical contact between the first metal layer and at least a portion of the second metal layer.

A memory cell, comprising:

• a substrate comprising one or more complementary metal-oxide semiconductor devices;
• a first insulator layer formed on the substrate;
• and
• a monolithic stack comprising multiple layers fabricated as part of a monolithic process over the first insulator layer, wherein the multiple layers comprise a first metal layer formed on a top surface of the substrate, a first conductive layer formed on the first metal layer, a second insulator layer, and a second metal layer, wherein a resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices, and wherein an electrical conductive material connects the first metal layer to at least a portion of the second metal layer.