Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsTakahiko Sasaki, Takeshi Yamaguchi
Life of this patent
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Abstract
A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.
Claims19
A semiconductor memory device, comprising
- a first wiring line extending in a first direction;
- a second wiring line extending in a second direction, the second direction intersecting the first direction;
- a variable resistance film disposed at an intersection of the first wiring line and the second wiring line;
- a channel body disposed at a first end of the first wiring line;
- a third wiring line electrically connected to the first wiring line via the channel body;
- a gate wiring line extending in the first direction and facing the channel body from the second direction;
- and
- a plurality of the first wiring lines aligned in the second direction,
- wherein the gate wiring line is disposed between the plurality of first wiring lines in the second direction.
A semiconductor memory device, comprising:
- a first wiring line extending in a first direction;
- a second wiring line extending in a second direction, the second direction intersecting the first direction;
- a variable resistance film disposed at an intersection of the first wiring line and the second wiring line;
- a channel body disposed at a first end of the first wiring line;
- a third wiring line electrically connected to the first wiring line via the channel body;
- and
- a gate wiring line extending in the first direction and facing the channel body from the second direction;
- wherein
- the gate wiring line is a columnar body extending from a position of a second end different from the first end of the first wiring line to a position of the channel body, in the first direction.
A semiconductor memory device, comprising:
- a semiconductor substrate;
- a first wiring line including a first channel body that extends in a first direction intersecting an upper surface of the semiconductor substrate;
- a second wiring line extending in a second direction, the second direction intersecting the first direction;
- a variable resistance film disposed at an intersection of the first wiring line and the second wiring line;
- a second channel body disposed at a first end of the first wiring line;
- a third wiring line electrically connected to the first wiring line via the second channel body;
- a first gate wiring line extending in the first direction and facing the first channel body from the second direction;
- and
- a second gate wiring line extending in the first direction and facing the second channel body from the second direction.
Dependencies are inferred from the claim text.