Methods of fabricating three-dimensional semiconductor devices

A method of fabricating a three-dimensional semiconductor device, comprising:

• providing a substrate with a peripheral circuit region and a cell array region;
• forming a peripheral structure on the peripheral circuit region of the substrate;
• forming an electrode structure on the cell array region of the substrate, the electrode structure comprising a lower electrode, a lower insulating planarized layer on the lower electrode, and upper electrodes and upper insulating layers vertically and alternatingly stacked on the lower insulating planarized layer, the lower insulating planarized layer being extended to cover the peripheral structure on the peripheral circuit region;
• and
• forming an upper insulating planarized layer to cover the electrode structure and the lower insulating planarized layer on the peripheral circuit region.

A method of fabricating a three-dimensional semiconductor device, comprising:

• providing a substrate having a peripheral circuit region and a cell array region;
• forming a peripheral structure on the peripheral circuit region of the substrate;
• sequentially forming a first sacrificial layer and a first insulating layer to cover the peripheral structure and the cell array region of the substrate, at least a portion of the first insulating layer protruding from the peripheral structure;
• forming an etch stop pattern to cover a top surface of the first insulating layer on the cell array region and to expose the protruding portion of the first insulating layer;
• planarizing the protruding portion of the first insulating layer using the etch stop pattern as an etch stop layer to provide a first insulating planarized layer;
• and
• forming a mold structure on the cell array region, the mold structure comprising second sacrificial layers and second insulating layers that are vertically and alternatingly stacked on the first insulating planarized layer.