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US 10,096,612 B2Granted
Three dimensional memory device having isolated periphery contacts through an active layer exhume process
AssigneeIntel Corporation
InventorsSri Sai Sivakumar Vegunta, Gowrisankar Damarla, Jian Zhou
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Abstract
A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.
Claims20
An apparatus, comprising:
- a semiconductor chip comprising an array region and a periphery region, said array region comprising a three dimensional stack of storage cells, the three dimensional stack of storage cells formed within the interconnect wiring of the semiconductor chip, said periphery region comprising contacts extending from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells, the periphery region being substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells and being part of the fully manufactured semiconductor chip, the periphery region composed of first dielectric having openings filled with second dielectric.
A method of forming a semiconductor chip, comprising:
- forming a three dimensional stack of storage cells, the three dimensional stack of storage cells comprising layers of conductive and/or semi-conductive material formed within the interconnect wiring of the semiconductor chip;
- exhuming the layers of conductive and/or semi-conductive material from a periphery region that resides adjacent to a storage region of the semiconductor chip formed within the interconnect wiring of the semiconductor chip and forming contacts within the periphery region that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells;
- completing manufacture of the semiconductor chip, the completely manufactured semiconductor chip including the periphery region being substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.
A computing system, comprising:
- a plurality of processing cores;
- a memory controller coupled to the processing cores, a system memory coupled to the memory controller;
- a non volatile storage device communicatively coupled to the memory controller, wherein at least one of the system memory and the non volatile storage device comprises a semiconductor chip comprising:
- an array region and a periphery region, said array region comprising a three dimensional stack of storage cells, the three dimensional stack of storage cells formed within the interconnect wiring of the semiconductor chip, said periphery region comprising contacts extending from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells, the periphery region being substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells and being part of the fully manufactured semiconductor chip, the periphery region composed of first dielectric having openings filled with second dielectric.
1 more element
Dependencies are inferred from the claim text.