US 10,096,610 B1 · Polysilicon doping controlled 3D NAND etching

Abstract

A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.

Claims25

Dependent claims

A semiconductor device, comprising:

a stacked semiconductor structure having an upper surface and a transversely opposed lower surface, the stacked semiconductor structure including:
a plurality of layers formed using a dielectric material;
and
a plurality of layers formed using a semiconductor material;
wherein each of the plurality of layers of semiconductor material are interleaved between layers of dielectric material;
wherein at least some of the plurality of layers of semiconductor material include a first dopant having one or more first dopant parameters;
and
wherein at least some of the plurality of layers of semiconductor material include a second dopant having one or more second dopant parameters, the one or more second dopant parameters different than the one or more first dopant parameters;
a plurality of channels, each of the channels penetrating the stacked semiconductor structure from the upper surface to the lower surface;
and
a recess about the periphery of each of the plurality of channels at each of the plurality of layers of semiconductor material in each of the plurality of channels.

8 more elements

A stacked semiconductor fabrication method, comprising:

interleaving each of a plurality of layers formed using a semiconductor material with a plurality of layers formed using a dielectric material to provide a stacked semiconductor structure having an upper surface and a lower surface;
wherein a first portion of the plurality of layers of semiconductor material include a first dopant having one or more first dopant parameters;
and
wherein a second portion of the plurality of layers of semiconductor material include a second dopant having one or more second dopant parameters, the one or more second dopant parameters different than the one or more first dopant parameters;
forming a plurality of channels through the stacked semiconductor structure, each of the plurality of channels extending from the upper surface to the lower surface of the stacked semiconductor structure;
and
removing a portion of at least some of the plurality of layers of semiconductor material forming a periphery of at least a portion of the plurality of channels to provide a recess about the periphery of each of the plurality of channels at each of the plurality of layers of semiconductor material.

4 more elements

An electronic device, comprising:

a stacked semiconductor structure having an upper surface and a transversely opposed lower surface, the stacked semiconductor structure including:
a plurality of layers formed using a dielectric material;
and
a plurality of layers formed using a semiconductor material;
wherein each of the plurality of layers of semiconductor material are interleaved between layers of dielectric material;
wherein at least some of the plurality of layers of semiconductor material include a first dopant having one or more first dopant parameters;
and
wherein at least some of the plurality of layers of semiconductor material include a second dopant having one or more second dopant parameters, the one or more second dopant parameters different than the one or more first dopant parameters;
a plurality of channels, each of the channels penetrating the stacked semiconductor structure from the upper surface to the lower surface;
and
a recess about the periphery of each of the plurality of channels at each of the plurality of layers of semiconductor material in each of the plurality of channels.

8 more elements

Dependencies are inferred from the claim text.

Polysilicon doping controlled 3D NAND etching

Life of this patent

Polysilicon doping controlled 3D NAND etching

Life of this patent

Abstract

Claims25