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US 10,096,608 B2Granted
Semiconductor device including memory cell array and power supply region
AssigneeRenesas Electronics Corporation
InventorsMasao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
Life of this patent
Estimating the term…
Abstract
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.
Claims4
A semiconductor device comprising:
- a memory cell including:
- a first conductivity type first MIS transistor coupled between a first voltage and a first node, and including a first gate electrode having first sidewalls on both sides thereof;
- a second conductivity type first MIS transistor coupled between the first node and a second voltage different from the first voltage, and including a second gate electrode having second sidewalls on both sides thereof;
- a second conductivity type second MIS transistor coupled between the first node and the second voltage in parallel with the second conductivity type first MIS transistor, and including a third gate electrode having third sidewalls on both sides thereof;
- a first conductivity type second MIS transistor coupled between the first voltage and a second node, and including a fourth gate electrode having fourth sidewalls on both sides thereof;
- a second conductivity type third MIS transistor coupled between the second node and the second voltage, and including a fifth gate electrode having fifth sidewalls on both sides thereof;
- a second conductivity type fourth MIS transistor coupled between the second node and the second voltage in parallel with the second conductivity type third MIS transistor, and including a sixth gate electrode having sixth sidewalls on both sides thereof;
- a second conductivity type fifth MIS transistor coupled between the first node and a first bit line, and including a seventh gate electrode having seventh sidewalls on both sides thereof;
- a second conductivity type sixth MIS transistor coupled between the second node and a second bit line, and including an eighth gate electrode having eighth sidewalls on both sides thereof;
- a second conductivity type seventh transistor coupled between the first node and a third bit line, and including a ninth gate electrode having ninth sidewalls on both sides thereof;
- and
- a second conductivity type eighth transistor coupled between the second node and a fourth bit line, and including a tenth gate electrode having tenth sidewalls on both sides thereof,
- the device further comprising:
- a monolithic first active region in which the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor are disposed;
- a second active region separated from the first active region, in which the second conductivity type second MIS transistor is disposed;
- a monolithic third active region in which the second conductivity type third MIS transistor and the second conductivity type sixth MIS transistor are disposed;
- and
- a fourth active region separated from the third active region, in which the second conductivity type fourth MIS transistor is disposed,
- wherein the first to fourth active regions are arranged side by side in a first direction and spaced from each other,
- wherein a first gate wiring extends in the first direction over the first active region,
- wherein a second gate wiring extends in the first direction over the first active region and the second active region,
- wherein a third gate wiring extends in the first direction over the third active region,
- wherein a fourth gate wiring extends in the first direction over the third active region and the fourth active region,
- wherein a fifth gate wiring extends in the first direction over the second active region,
- wherein a sixth gate wiring extends in the first direction over the fourth active region,
- wherein the seventh transistor is disposed in the second active region,
- wherein the eighth transistor is disposed in the fourth active region,
- wherein the first active region extends in a second direction intersecting with the first direction with a same first width,
- wherein the second active region extends in a second direction with a same second width,
- wherein the third active region extends in a second direction with a same third width, and
- wherein the fourth active region extends in the second direction with a same fourth width.
28 more elements
Dependencies are inferred from the claim text.