Three-dimensional stacked junctionless channels for dense SRAM
AssigneeInternational Business Machines Corporation
InventorsMichael A. Guillorn, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla
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Abstract
A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.
Claims20
A structure, comprising:
- a first channel region forming an n-channel device;
- a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation;
- a gate positioned around the stacked n-channel device and p-channel device;
- and
- at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device;
- wherein each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted;
- and
- wherein the first channel region forming an n-channel device forms a junctionless NFET device, and wherein the second channel region forming a p-channel device forms a junctionless PFET device.
A unit cell for a transistor structure, the unit cell comprising:
- a junctionless PFET device comprising at least one layer of a p-doped material;
- a junctionless NFET device comprising at least two layers of an n-doped material stacked on the junctionless PFET device;
- an inverter gate wrapped around the stacked junctionless PFET device and junctionless NFET device;
- a passgate wrapped around the stacked junctionless PFET device and junctionless NFET device;
- a first set of contacts extending to the p-doped material of the junctionless PFET device;
- a second set of contacts extending to the n-doped material of the junctionless NFET device;
- a voltage input contact extending to the inverter gate;
- and
- a wordline contact extending to the passgate.
A structure, comprising:
- a first channel region forming an n-channel device;
- a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation;
- a gate positioned around the stacked n-channel device and p-channel device;
- and
- at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device;
- wherein each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted;
- and
- wherein the first channel region forming an n-channel device comprises at least two layers of an n-doped material, and wherein the second channel region forming a p-channel device comprises at least one layer of a p-doped material.
Dependencies are inferred from the claim text.