Methods of forming a gate structure-to-source/drain conductive contact on vertical transistor devices and the resulting transistor devices

A method of forming a gate structure-to-source/drain conductive contact structure between a first vertical transistor and a second vertical transistor, the method comprising:

• forming a continuous layer of a bottom spacer material above first and second bottom source/drain (S/D) regions of said first and second vertical transistors, respectively, and above an isolation region positioned in a semiconductor substrate and laterally between said first and second bottom S/D regions;
• forming a continuous gate insulation layer above said continuous layer of said bottom spacer material;
• performing at least one first etching process to remove a portion of said continuous gate insulation layer and a portion of said continuous layer of said bottom spacer material so as to thereby form a gate-to-source/drain contact opening that exposes a portion of said first bottom S/D region;
• forming a continuous conductive gate electrode material layer above said first and second bottom S/D regions and within said gate-to-source/drain contact opening;
• and
• performing at least one second etching process to remove at least portions of said continuous gate electrode material layer and said gate insulation layer so as to form first and second separate gate structures for said first and second vertical transistors, respectively, wherein a portion of said second gate structure is positioned within said gate-to-source/drain contact opening, thereby conductively coupling said second gate structure to said first bottom S/D region.

An integrated circuit product comprising:

• a first vertical transistor comprising:
• a first vertically oriented channel semiconductor (VOCS) structure;
• a first bottom source/drain (S/D) region positioned around said first VOCS structure;
• a first bottom spacer positioned above said first bottom S/D region and around said first VOCS structure, said first bottom spacer having a gate-to-source/drain contact opening formed therein;
• and
• a first gate electrode structure positioned above said first bottom spacer and around said first VOCS structure;
• and
• a second vertical transistor comprising:
• a second vertically oriented channel semiconductor (VOCS) structure;
• a second bottom source/drain (S/D) region positioned around said second VOCS structure;
• a second bottom spacer positioned above said second bottom S/D region and around said second VOCS structure;
• and
• a second gate electrode structure positioned above said second bottom spacer and around said second VOCS structure, wherein a portion of said second gate structure is positioned within said gate-to-source/drain contact opening, thereby conductively coupling said second gate structure to said first bottom S/D region.