Selective SAC capping on fin field effect transistor structures and related methods

A static random access memory (SRAM) cell comprising:

• a plurality of fin field effect transistor structures (FinFETs) including:
• a substrate,
• a plurality of gates disposed on the substrate,
• a plurality of source/drain regions within the substrate adjacent to each of the gates, and
• a dielectric disposed between each gate and the adjacent source/drain regions;
• a dielectric capping layer disposed on at least a first one of the plurality of gates, wherein no dielectric capping layer is disposed on a second one of the plurality of gates;
• a first local interconnect electrically connected to, and in direct contact with, an upper surface of the second one of the plurality of gates, wherein the dielectric capping layer disposed on the first one of the plurality of gates electrically separates the first local interconnect from the first one of the at least two gates;
• and
• a second local interconnect electrically connected to one of the source/drain regions adjacent to the second one of the plurality of gates, and wherein the second local interconnect contacts the dielectric capping layer.

An integrated circuit structure comprising:

• a fin field effect transistor (FinFET) structure including:
• a substrate;
• at least two gates disposed on the substrate;
• a plurality of source/drain regions within the substrate adjacent to each of the gates;
• a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate;
• a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates;
• and
• a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates, and
• wherein a portion of an upper surface of the second one of the at least two gates is free from the local interconnect and the dielectric capping layer.