MTP memory for SOI process

A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:

• an ultra-thin silicon-on-insulator (SOI) substrate having a body substrate disposed over a base substrate, wherein a very thin buried oxide (BOX) layer is disposed between the base substrate and the body substrate;
• an active region defined in the SOI substrate, wherein the active region comprises a transistor region and a capacitor region;
• a gate structure disposed on the SOI substrate, the gate structure comprises a gate electrode layer disposed over a gate dielectric layer, wherein the gate structure extends continuously across the active region to overlap the transistor region and the capacitor region, wherein a first portion of the gate structure defines a transistor gate and a second portion of the gate structure defines a capacitor gate;
• a first polarity type device well disposed in the base substrate, wherein the device well traverses the transistor region and the capacitor region, the device well underlaps the transistor gate and the capacitor gate;
• and
• first and second doped regions disposed within the capacitor region, wherein the first doped region is disposed in the body substrate and the second doped region is disposed in the base substrate within the device well, wherein the first and the second doped regions comprise first polarity type dopants, wherein the first and the second doped regions comprise a higher dopant concentration of first polarity type dopants relative to the device well.

A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:

• a fully depleted silicon-on-insulator (FDSOI) substrate having a body substrate disposed over a base substrate, wherein the FDSOI substrate includes a thin buried oxide (BOX) layer disposed between the base substrate and the body substrate;
• an active region defined in the FDSOI substrate, wherein the active region comprises a transistor region and a capacitor region;
• a gate structure disposed on the FDSOI substrate, the gate structure comprises a gate electrode layer disposed over a gate dielectric layer, wherein the gate structure extends continuously across the active region to overlap the transistor region and the capacitor region, wherein a first portion of the gate structure defines a transistor gate and a second portion of the gate structure defines a capacitor gate, wherein the transistor gate and the capacitor gate comprise a common gate electrode layer and a common gate dielectric layer;
• a first polarity type device well disposed in the base substrate, wherein the device well extends laterally to traverse the transistor region and the capacitor region, the device well underlaps the transistor gate and the capacitor gate;
• first and second doped regions disposed within the capacitor region, wherein the first doped region is disposed in the body substrate and the second doped region is disposed in the base substrate within the device well, wherein
• the first and the second doped regions are first polarity type doped regions comprising a higher dopant concentration of first polarity type dopants relative to the device well, and
• the second doped region extends to a depth shallower than a depth of the device well;
• and
• wherein a contact region is defined in the base substrate within the device well, wherein the contact region is displaced away from the transistor region and the capacitor region.