Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process

An apparatus, comprising:

• a first transistor, comprising:
• a first semiconductor fin with a top, a first sidewall, and a second sidewall opposite the first sidewall;
• a first gate dielectric structure that wraps around at least a portion of the first sidewall, at least a portion of the second sidewall, and at least a portion of the top of the first semiconductor fin and is in contact with the first semiconductor fin, the first gate dielectric structure comprising a first layer of a first dielectric material having a first thickness and being in contact with the top, the first sidewall and the second sidewall of the first semiconductor fin, and the first gate dielectric structure comprising a second layer of a second dielectric material on a portion of the first layer of the first dielectric material in contact with the top, the first sidewall and the second sidewall of the first semiconductor fin;
• a first gate electrode structure that wraps around at least a portion of the first sidewall, at least a portion of the second sidewall, and at least a portion of the top of the first semiconductor fin, wherein at least a portion of the first gate dielectric structure is between at least a portion of the first semiconductor fin and the at least a portion of the first gate electrode structure;
• and
• a first n type source region to a first side of the first gate electrode structure;
• and
• a first n type drain region to a second side of the first gate electrode structure, the second side of the first gate electrode structure being opposite the first side of the first gate electrode structure;
• and
• a second transistor isolated from the first transistor, the second transistor comprising:
• a second semiconductor fin with a top, a first sidewall, and a second sidewall opposite the first sidewall;
• a second gate dielectric structure that wraps around at least a portion of the first sidewall, at least a portion of the second sidewall, and at least a portion of the top of the second semiconductor fin and is in contact with the second semiconductor fin, the second gate dielectric structure comprising a first layer, the first layer of the second gate dielectric structure comprising the first dielectric material and having a second thickness greater than the first thickness of the first layer of the first gate dielectric structure, and the first layer of the second gate dielectric structure in contact with the top, the first sidewall and the second sidewall of the second semiconductor fin, and the second gate dielectric structure comprising a second layer, the second layer of the second gate dielectric structure comprising the second dielectric material on a portion of the first layer of the second gate dielectric structure in contact with the top, the first sidewall and the second sidewall of the second semiconductor fin;
• a second gate electrode structure that wraps around at least a portion of the first sidewall, at least a portion of the second sidewall, and at least a portion of the top of the second semiconductor fin, wherein at least a portion of the second gate dielectric structure is between at least a portion of the second semiconductor fin and the at least a portion of the second gate electrode structure;
• a second n type source region to a first side of the second gate electrode structure;
• and
• a second n type drain region to a second side of the second gate electrode structure, the second side of the second gate electrode structure being opposite the first side of the second gate electrode structure.