Methods for fabricating fin field effect transistors

A method for fabricating a fin field effect transistor (FinFET), comprising:

• forming a first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin;
• forming a dummy gate strip over the insulator to cross over portions of the first semiconductor fin and the second semiconductor fin;
• removing a portion of the dummy gate strip to form an opening, wherein the opening is disposed between the first semiconductor fin and the second semiconductor fin and a top critical dimension of the opening is smaller than a bottom critical dimension of the opening;
• filling a first dielectric material in the opening, wherein an air gap is formed in the first dielectric material simultaneously during filling the first dielectric material in the opening;
• removing a portion of the first dielectric material to expose the air gap, so as to form a first dielectric layer with a slit therein;
• removing the remained dummy gate strip;
• forming a second dielectric layer to fill the slit;
• and
• forming a first gate and a second gate to cross over portions of the first semiconductor fin and the second semiconductor fin respectively, wherein the first and second gates are electrically insulated from each other by the first dielectric layer comprising the second dielectric layer therein.

A method for fabricating a fin field effect transistor (FinFET), comprising:

• patterning a substrate to form a first semiconductor fin, a second semiconductor fin and a trench between the first semiconductor fin and the second semiconductor fin, wherein the first semiconductor fin is extended in a first direction and has a height in a second direction perpendicular to the first direction;
• forming an insulator in the trench;
• forming a first dummy gate and a second dummy gate on the first semiconductor fin and the second semiconductor fin respectively, wherein an opening is formed between the first dummy gate and the second dummy gate over the insulator;
• forming a first dielectric material in the opening, wherein the first dielectric material is formed with an air gap therein;
• removing a portion of the first dielectric material to form a first dielectric layer, and thus the air gap is exposed to form a slit in the first dielectric layer;
• removing the first dummy gate and the second dummy gate;
• forming a second dielectric layer to fill the slit, wherein a bottom portion of the first dielectric layer is disposed below a bottom portion of the second dielectric layer, wherein the first dielectric layer is disposed over and partially overlapped with the insulator in the second direction;
• and
• forming a first gate and a second gate on the first semiconductor fin and the second semiconductor fin respectively, wherein the first gate and the second gate are electrically insulated by the first dielectric layer comprising the second dielectric layer therein.