Semiconductor device structure having a plurality of gate structures

A semiconductor device structure, comprising:

• a substrate having a first source region, a second source region, a first drain region, and a second drain region;
• a first metal gate stack over the substrate and between the first source region and the first drain region, wherein the first metal gate stack includes a gate dielectric layer, a work function layer, and a gate electrode layer, wherein the first metal gate stack has a first thickness measured as a vertical distance above a top surface of the substrate to a top surface of the work function layer of the first metal gate stack;
• a second metal gate stack over the substrate and between the second source region and the second drain region, wherein the second metal gate stack includes the gate dielectric layer, the work function layer, and the gate electrode layer, and wherein the second metal gate stack has a second thickness measured as a vertical distance above the top surface of the substrate to a top surface of the work function layer of the second metal gate stack, wherein the first and second thickness are substantially equal, and wherein a first gate width of the first metal gate stack is less than a second gate width of the second metal gate stack;
• a first spacer surrounding the first metal gate stack and having a first thickness measured as a vertical distance from the top surface of the substrate;
• and
• a second spacer surrounding a portion of the second metal gate stack and having a second thickness measured as a vertical distance from the top surface of the substrate, wherein the first thickness of the first spacer is greater than the second thickness of the second spacer, and wherein the work function layer of the second metal gate stack extends above the second spacer, and wherein the work function layer is one of an n-type metal or a p-type metal in both of the first and second metal gate stacks.

A semiconductor device structure, comprising:

• a semiconductor device structure, comprising:
• a substrate having a first source region, a second source region, a first drain region, and a second drain region;
• a first gate stack over the substrate and between the first source region and the first drain region, wherein the first gate stack forms a gate of a first type of transistor, wherein the first type of transistor is one of an NMOS transistor or a PMOS transistor;
• a second gate stack over the substrate and between the second source region and the second drain region, wherein a first gate width of the first gate stack is less than a second gate width of the second gate stack and wherein a third thickness of the first gate stack is substantially equal to a fourth thickness of the second gate stack, each of the third and fourth thicknesses defined as a vertical distance above a top surface of the substrate, wherein the second gate stack forms a gate of the first type of transistor;
• a first spacer surrounding the first gate stack;
• a second spacer surrounding the second gate stack;
• and
• a dielectric layer over the substrate, the first spacer and the second spacer and surrounding the first gate stack and the second gate stack, wherein the dielectric layer adjacent the first spacer and adjacent the second spacer and the first spacer each have a same first thickness, and the first thickness is greater than a second thickness of the second spacer, wherein the first and second thicknesses are defined as a vertical distance above the top surface of the substrate.