Method for fabricating a semiconductor integrated chip

A method for fabricating a compound semiconductor integrated chip, sequentially comprising steps of:

• growing at least one compound semiconductor epitaxial layer on a substrate of a chip;
• fabricating at least one compound semiconductor electronic device on the substrate using the at least one compound semiconductor epitaxial layer;
• depositing at least one second metal layer made essentially of Au above the at least one compound semiconductor epitaxial layer to form an electrical connection to at least one of the at least one compound semiconductor electronic device, and also to form at least one second pad;
• depositing a SiN layer above the at least one second metal layer for passivation or protection of the at least one compound semiconductor electronic device;
• depositing a dielectric layer above the SiN layer;
• forming at least one dielectric layer via hole penetrating through the dielectric layer for the electrical contact to the at least one second pad;
• and
• depositing a first metal layer made essentially of Cu on the dielectric layer forming at least one first pad on the dielectric layer, the first metal layer extending from each of the at least one first pad into the at least one dielectric layer via hole and connecting to the at least one second pad, where the first metal layer extends from at least one of the at least one first pad three-dimensionally over at least one of the at least one compound semiconductor device, then into the at least one dielectric layer via hole and connects to the at least one second pad.