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US 10,096,563 B2Granted
Semiconductor package and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wei Chen, An-Jhih Su
Life of this patent
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Abstract
A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.
Claims20
A semiconductor package comprising:
- a first insulator layer;
- a backside redistribution layer over the first insulator layer;
- a second insulator layer over the backside redistribution layer;
- a surface-mount device (SMD) over the second insulator layer, with the second insulator layer sandwiched between a bottom surface of the SMD and the backside redistribution layer;
- and
- a solder extending from the SMD's bottom surface, through the second insulator layer, to the backside redistribution layer;
- first and second pads that connect the SMD to the backside redistribution layer and are spaced apart from each other in a longitudinal direction, wherein the first pad has
- an end edge extending in a lateral direction transverse to the longitudinal direction,
- parallel first and second side edges extending respectively from opposite ends of the end edge in a direction longitudinally away from the second pad, and
- a notch that interrupts the laterally-extending end edge by extending longitudinally inward from the end edge, the notch having an open end at the pad's end edge and a closed end longitudinally opposite the open end, and is located between the first and second side edges, to form (i) a first tab bounded by a first side of the notch and the end edge and the first side edge, and (ii) a second tab bounded by a second side of the notch and the end edge;
- and
- first and second solders that are electrically connected to each other only through the pad and that respectively join the first and second tabs to the SMD, wherein the SMD covers only a portion of the first tab and only a portion of the second tab and does not extend directly over the notch's closed end.
9 more elements
A semiconductor package comprising:
- parallel upper and lower redistribution layers;
- a chip that is located between the upper and lower redistribution layers and has
- upper and lower ends respectively adjacent the upper and lower redistribution layers, and
- an electrical contact, at the chip's upper end, that directly and physically contacts the upper redistribution layer;
- a surface mount device (SMD) that is located between the upper and lower redistribution layers and has
- a lower end adjacent the lower redistribution layer,
- an upper end spaced downward from the upper redistribution layer, and
- an electrical contact, at the SMD's lower end, that directly and physically contacts the lower redistribution layer;
- and
- a via that extends from the upper redistribution layer to the lower redistribution layer and directly and physically contacts both the upper and lower redistribution layer, to enable an electrical path extending from the SMD's electrical contact, through the lower redistribution layer, through the via, and through the upper redistribution layer to the chip's electrical contact.
7 more elements
A method of making a semiconductor package, the method comprising:
- providing parallel upper and lower redistribution layers;
- providing a chip that is located between the upper and lower redistribution layers and has
- upper and lower ends respectively adjacent the upper and lower redistribution layers, and
- an electrical contact, at the chip's upper end, that directly and physically contacts the upper redistribution layer;
- providing a surface mount device (SMD) that is located between the upper and lower redistribution layers and has
- a lower end adjacent the lower redistribution layer,
- an upper end spaced downward from the upper redistribution layer, and
- an electrical contact, at the SMD's lower end, that directly and physically contacts the lower redistribution layer;
- and
- providing a via that extends from the upper redistribution layer to the lower redistribution layer and directly and physically contacts both the upper and lower redistribution layer, to enable an electrical path extending from the SMD's electrical contact, through the lower redistribution layer, through the via, and through the upper redistribution layer to the chip's electrical contact.
7 more elements
Dependencies are inferred from the claim text.