Fan-out semiconductor package

A fan-out semiconductor package comprising:

• a first interconnection member having first and second through-holes spaced apart from each other;
• a processor chip disposed in the first through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
• a memory chip disposed in the second through-hole of the first interconnection member, having an active surface having connection pads disposed thereon, and including a plurality of dies stacked on each other;
• an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip;
• and
• a second interconnection member disposed on the first interconnection member, the active surface of the memory chip, and the active surface of the processor chip,
• wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the processor chip and the connection pads of the memory chip,
• the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member,
• the first interconnection member includes a first insulating layer, a first redistribution layer in contact with the second interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
• the second redistribution layer is disposed on a level between the active surface and the inactive surface of the processor chip.

A fan-out semiconductor package comprising:

• a first interconnection member having a through-hole;
• a processor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
• a memory chip disposed in the through-hole of the first interconnection member, having an active surface having connection pads disposed thereon, and including a plurality of dies stacked on each other;
• an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip;
• and
• a second interconnection member disposed on the first interconnection member, the active surface of the memory chip, and the active surface of the processor chip,
• wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the processor chip and the connection pads of the memory chip,
• the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member,
• the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
• the first redistribution layer is disposed on a level between the active surface and the inactive surface of the processor chip.