Back to results
US 10,096,557 B2Granted
Tiled-stress-alleviating pad structure
AssigneeGlobalfoundries Inc.
InventorsEkta Misra, Mukta G. Farooq, Krishna Tunga
Life of this patent
Estimating the term…
Abstract
Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.
Claims10
A semiconductor device comprising:
- a tiled-stress-alleviating pad structure in contact with a last level of an integrated circuit having a dielectric layer and a metal wiring, the last level is located on a substrate structure, wherein the tiled-stress-alleviating pad structure comprises a plurality of tiles, the plurality of the tiles of the tiled-stress-alleviating pad structure having a set geometry and a set distance between immediately adjacent tiles, and are uniformly spaced apart from each other by the set distance,
- wherein the tiled-stress-alleviating pad structure comprises a first set of tiles and a second set of tiles, the first set of tiles overlying a last level metal wiring, and the second set of tiles extending laterally over a last level dielectric layer and the last level metal wiring, and wherein an area of the second set of tiles is less than an area of the first set of tiles.
A semiconductor device comprising:
- a tiled-stress-alleviating pad structure in contact with a last level of an integrated circuit having a dielectric layer and a metal wiring, the last level is located on a substrate structure, wherein the tiled-stress-alleviating pad structure comprises a plurality of tiles, the plurality of the tiles of the tiled-stress-alleviating pad structure having a set geometry and a set distance of from about 1,500 nm to about 2,000 nm between immediately adjacent tiles, and are uniformly spaced apart from each other by the set distance.
A semiconductor device comprising:
- a tiled-stress-alleviating pad structure in contact with a last level of an integrated circuit having a dielectric layer and a metal wiring, the last level is located on a substrate structure, wherein the tiled-stress-alleviating pad structure comprises a plurality of tiles, the plurality of the tiles of the tiled-stress-alleviating pad structure having a set geometry and a set distance between immediately adjacent tiles, and are uniformly spaced apart from each other by the set distance, wherein the area of each tile of the plurality of tiles is within a range of about 3,000 nm2 to about 30,000 nm2.
Dependencies are inferred from the claim text.