Semiconductor device having an epitaxial layer and manufacturing method thereof

#The disclosure of Japanese Patent Application No. 2016-115296 filed on Jun. 9, 2016 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

#The present invention relates to a semiconductor device and a manufacturing method therefor, and is preferably applicable to a semiconductor device including, for example, an epitaxial layer and a mark for superposition inspection.

#In a semiconductor device including a high withstand voltage semiconductor element, a plurality of pn junction structures are formed in a semiconductor substrate including a silicon substrate. When a pnp junction structures are formed, an n-type region is formed by injecting n-type impurities into the surface of a p-type silicon substrate. Then, a p-type region (an epitaxial layer) is formed using an epitaxial growth method, on the surface of its n-type region.

#FIG. 1 is a plan view showing a semiconductor device according to an embodiment 1.

#FIG. 2 is a cross sectional view taken along a line II-II illustrated in FIG. 1, in the same embodiment.

#FIG. 3 is a cross sectional view showing one process of a manufacturing method of the semiconductor device, in the same embodiment.

#Embodiment 1

#Descriptions will now be made to a semiconductor device according to an embodiment 1. As illustrated in FIG. 1 and FIG. 2, on a semiconductor substrate SUB, an element region ETR and a mark region MKR are defined. The semiconductor substrate SUB includes a silicon substrate SB (a crystal substrate) and a p-type epitaxial layer PEL (a crystal layer). The p-type epitaxial layer PEL is formed over a surface of the silicon substrate SB, using an epitaxial growth method. In the element region ETR, an N-type injection region NIR is formed over a predetermined depth from the surface of the silicon substrate SB in advance, for forming a pn junction.

#An element isolation region EIR is formed in the p-type epitaxial layer PEL positioned in the element region ETR. In the element isolation region EIR, an element isolation film is formed in a trench. In the element region ETR, for example, a high withstand voltage NMOS transistor HVNT is formed, as a high withstand voltage semiconductor element. A high withstand voltage NMOS transistor HVNT includes an N-type impurity region NDR and a high concentration N-type impurity region NHDR as drains, an N-type impurity region NSR as a source, and a gate electrode GE.