Fan-out semiconductor package
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsHan Kim, Eun Jung Jo, Jung Ho Shim
Life of this patent
Estimating the term…
Abstract
A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.
Claims20
A semiconductor package comprising:
- a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface;
- a first encapsulant encapsulating at least portions of the first semiconductor chip;
- a connection member disposed on the first encapsulant and the first active surface of the first semiconductor chip and including first vias and a first redistribution layer electrically connected to the first connection pads through the first vias;
- a second semiconductor chip having a second active surface having second connection pads disposed thereon, and a second inactive surface opposing the second active surface and attached to the connection member;
- a second encapsulant covering at least portions of the connection member and encapsulating at least portions of the second semiconductor chip;
- a second redistribution layer disposed on the second encapsulant and the second active surface of the second semiconductor chip;
- second vias penetrating through the second encapsulant and electrically connecting the second connection pads and the second redistribution layer to each other;
- and
- third vias penetrating through the second encapsulant and electrically connecting the first redistribution layer and the second redistribution layer to each other.
A semiconductor package comprising:
- a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface;
- a first encapsulant encapsulating at least portions of the first semiconductor chip;
- a second semiconductor chip having a second active surface having second connection pads disposed thereon, and a second inactive surface opposing the second active surface;
- a connection member disposed between the first encapsulant and the first active surface of the first semiconductor chip, and the second encapsulant and the second inactive surface of the second semiconductor chip, the connection member including a first insulating layer, first vias penetrating through the first insulating layer and being in contact with the first connection pads of the first semiconductor chip, and a first redistribution layer electrically connected to the first connection pads through the first vias;
- a second encapsulant covering at least portions of the connection member and encapsulating at least portions of the second semiconductor chip;
- a second redistribution layer disposed on the second encapsulant and the second active surface of the second semiconductor chip;
- second vias penetrating through the second encapsulant and electrically connecting the second connection pads and the second redistribution layer to each other;
- and
- third vias penetrating through the second encapsulant and electrically connecting the first redistribution layer and the second redistribution layer to each other.
Dependencies are inferred from the claim text.