Electronic component of integrated circuitry and a method of forming a conductive via to a region of semiconductor material

#Embodiments disclosed herein pertain to electronic components of integrated circuitry and to methods of forming a conductive via to a region of semiconductor material.

#Embodiments of the invention were motivated in addressing trade-offs in attaining high device on-current (Ion) at the expense of undesired current leakage in recessed access devices.

#A recessed access device is a field effect transistor having its gate construction buried within a trench formed in semiconductive material. The gate construction includes a gate insulator which lines the trench and conductive gate material within the trench laterally inward of the gate insulator. A source/drain region is formed in outermost regions of the semiconductive material on each of opposing sides of the trench. When the two source/drain regions are at different voltages and a suitable voltage is applied to the conductive gate material, current (Ion) flows through the semiconductive material between the source/drain regions along the trench sidewalls and around the base of the trench (i.e., a conductive channel forms through which current flows between the two source/drain regions). Voltage of the source/drain regions is typically controlled through a respective conductive via that makes electrically coupling contact with the respective source/drain region. To minimize contact resistance, the elevationally outermost portions of the source/drain regions may be provided with a high conductivity dopant implant, for example phosphorus (for n-type) implanted at 1 to 8 keV at a dose of 1×1014 atoms/cm2 to 4×1014 atoms/cm2 to provide a conductivity-increasing implant of greater than 1×1020 atoms/cm3. This renders the elevationally outermost portion of the source/drain region highly conductive, thereby reducing contact resistance but at the expense of increasing gate induced drain leakage (GIDL) or off current (Ioff). GIDL is a negative attribute associated with field effect transistors and can be problematic with recessed access devices or other devices or applications where leakage is a concern. For example, DRAM access devices can suffer from charge leakage due to increase in GIDL. High dose implants can increase Ion but also can increase GIDL.

#FIG. 1 is a diagrammatic sectional view of a vertical cross-section of a substrate fragment comprising an electronic component of integrated circuitry in accordance with an embodiment of the invention.

#FIG. 2 is a diagrammatic sectional view of a vertical cross-section of a substrate fragment comprising an electronic component of integrated circuitry in accordance with an alternate embodiment the invention.

#FIG. 3 is a diagrammatic sectional view of a vertical cross-section of a substrate fragment comprising an electronic component of integrated circuitry in accordance with an alternate embodiment the invention.

#Embodiments of the invention encompass an electronic component of integrated circuitry. In one embodiment the component is a field effect transistor and in one such embodiment is a recessed access device. Embodiments of the invention encompass other electronic components whether existing or yet-to-be developed.

#Some embodiments of the invention are initially described with reference to FIG. 1, which shows a substrate fragment 10 comprising a base substrate 12 which may comprise a semiconductor substrate. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Base substrate 12 may comprise any one or more of conductive (i.e., electrically herein), semiconductive, or insulative/insulator (i.e., electrically herein) material(s). Example substrate 12 comprises semiconductor material 14, for example suitably doped monocrystalline silicon, polysilicon, sapphire, or silicon-germanium, having trench isolation regions 16 formed therein. Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples. Example trench isolation material is silicon dioxide which may be lined with silicon nitride. Additionally and or alternately, conductive isolation structures might be within trench isolation regions 16.

#FIG. 1 shows two electronic components 18 and 20 of integrated circuitry in accordance with an embodiment of the invention. Such are shown as having been fabricated relative to example substrate 12, although other substrates may be used. Further, each is shown as being in the form of a field effect transistor, and more specifically in one embodiment as a recessed access device. Components 18 and 20 in the depicted example are mirror images of one another and share a source/drain region/terminal as described below, although such is of course not required. Regardless, an electronic component of integrated circuitry in accordance with an embodiment of the invention comprises a substrate (e.g., substrate 12) comprising at least two terminals. Electronic component 18 comprises at least three terminals in the form of a conductive gate 22 in a trench 23 in semiconductor material 14 and a pair of source/drain regions 26 and 28 in elevationally outer portions of semiconductor material 14 on opposing sides of trench 23 (the three terminals being parts 22, 26, and 28). In this document, “elevational”, “upper”, “lower”, “top”, “bottom”, “above, “below”, “under” and “beneath” are generally with reference to the vertical direction. “Horizontal” refers to a general direction (i.e., within 10 degrees) along a primary surface relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space.