US 10,096,544 B2Granted

Semiconductor interconnect structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChih-Ming Lai, Wen-Chun Huang, Ru-Gun Liu, Pi-Tsung Chen

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Abstract

The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

Claims20

Dependent claims

A semiconductor device, comprising:

a first conductive line feature having a topmost surface, wherein the first conductive line feature is formed in a first dielectric layer disposed on a semiconductor substrate having a plurality of microelectronic components formed in the semiconductor substrate;
a first via conductor disposed over the first conductive line feature,
wherein a first portion of a bottom surface of the first via conductor interfaces a portion of the topmost surface of the first conductive line feature and a second portion of the bottom surface of the first via conductor interfaces the first dielectric layer;
a second via conductor disposed over the first via conductor and the second via conductor having a bottom surface, wherein a first portion of the bottom surface of the second via conductor interfaces a top surface of the first via conductor and a second portion of the second via conductor interfaces a second dielectric layer adjacent the first via conductor;
and
a second conductive line feature disposed over and interfacing a top surface of the second via conductor,
wherein the second conductive line feature has a bottommost surface with a first portion interfaces a first portion of a top surface of the second via conductor, wherein a second portion of the top surface of the second via conductor interfaces a third dielectric layer, the third dielectric layer over the second dielectric layer, and wherein the first portion of the top surface of the second via conductor is coplanar with the second portion of the top surface of the second via conductor;
and
wherein the first conductive line feature and the second conductive line feature are offset such that the topmost surface of the first conductive line feature is not directly underneath the bottommost surface of the second conductive line feature;
wherein the interface of the first portion of the top surface of the second via conductor and the bottommost surface of the second conductive line feature has a first length, and the interface between the first portion of the bottom surface of the first via conductor and the portion of the topmost surface of the first conductive line feature has a second length, the first length greater than the second length;
and
the first conductive line feature is in a first interconnect layer denoted Mx of an interconnect structure of the semiconductor device;
the second conductive line feature is in a second interconnect layer of the interconnect structure of the semiconductor device above the first interconnect layer denoted Mx+1, wherein x is equal to an whole number equal to 1;
and
wherein the first conductive line feature, the first via conductor, the second via conductor and the second conductive line feature provide electrical routing between the microelectronic components of the semiconductor substrate.

12 more elements

A semiconductor structure, comprising:

a semiconductor substrate having an interconnect structure disposed thereon, the interconnect structure providing interconnections between features formed in the semiconductor substrate, the interconnect structure including:
a first interconnect layer containing a first metal line in a first dielectric layer and extending parallel to a top surface of the semiconductor substrate providing electrical routing in a horizontal direction;
a second dielectric layer located over the first metal line and the first dielectric layer;
a first sub-via conductor having a planar first bottommost surface, the planar first bottommost surface having a first portion interfacing to a topmost surface of the first metal line and a second portion of the planar first bottommost surface interfacing the first dielectric layer;
a second sub-via conductor having a planar second bottommost surface, a first portion of the planar second bottommost surface interfacing to the first sub-via conductor and a second portion of the planar second bottommost surface interfacing the second dielectric layer, the second sub-via conductor being different from the first sub-via conductor, wherein the first sub-via conductor is positioned above the first metal line and the second sub-via conductor is positioned above the first sub-via conductor;
and
a second interconnect layer located over the second dielectric layer and containing a second metal line extending parallel to the top surface of the semiconductor substrate and providing routing in the horizontal direction and interfacing the second sub-via conductor,
wherein a first portion of a planar topmost surface of the second sub-via conductor interfaces a first portion of a bottommost surface of the second metal line, and a second portion of the planar topmost surface of the second sub-via conductor interfaces a third dielectric layer, wherein a first length of the first portion of the planar topmost surface of the second sub-via conductor is greater than a second length of the first portion of the planar first bottommost surface of the first sub-via conductor that interfaces the topmost surface of the first metal line;
wherein the second interconnect layer is an adjacent interconnect layer to the first interconnect layer;
and
wherein a topmost surface of the first metal line is not directly underneath the bottommost surface of the second metal line.

8 more elements

A semiconductor device, comprising:

a first conductive component disposed in a first dielectric material over a semiconductor substrate, wherein the first conductive component is a first metal line providing a horizontal routing of an electrical signal;
a first via conductor in a third dielectric material and disposed over the first conductive component,
wherein a first portion of a bottom surface of the first via conductor interfaces a first portion of a topmost surface of the first conductive component,
wherein a second portion of the bottom surface of the first via conductor interfaces the first dielectric material, wherein the first portion and the second portion of the bottom surface of the first via conductor are coplanar;
and
wherein a second portion of the topmost surface of the first conductive component interfaces a second dielectric material disposed over the first dielectric material and under the third dielectric material, wherein the second dielectric material has a different composition than the first dielectric material and the third dielectric material and the first portion of the topmost surface of the first conductive component is coplanar with the second portion of the topmost surface of the first conductive component;
a second via conductor disposed in a fifth dielectric material over the third dielectric material wherein the second via conductor is electrically coupled to the first via conductor,
wherein a first portion of a top surface of the first via conductor interfaces a first portion of a bottom surface of the second via conductor,
wherein a second portion of the top surface of the first via conductor interfaces a fourth dielectric material under the fifth dielectric material and over the third dielectric material, wherein the first portion of the top surface of the first via conductor and the second portion of the top surface of the first via conductor are coplanar;
and
wherein a second portion of the bottom surface of the second via conductor interfaces the third dielectric material, wherein the first portion of the bottom surface of the second via conductor is coplanar with the second portion of the bottom surface of the second via conductor;
and
wherein the first and second via conductors provide a vertical routing of the electrical signal between the first conductive component and a second conductive component;
the second conductive component disposed in a seventh dielectric material over and electrically coupled to the first conductive component wherein the second conductive component is electrically coupled to the first conductive component by the first via conductor and the second via conductor, wherein the second conductive component is a second metal line providing a horizontal routing of the electrical signal;
wherein a first portion of a top surface of the second via conductor interfaces a first portion of a bottommost surface of the second conductive component,
wherein a second portion of the top surface of the second via conductor interfaces a sixth dielectric material, the sixth dielectric material interposing the fifth dielectric material and the seventh dielectric material and having a different composition than each of the fifth dielectric material and the seventh dielectric material, the first portion of the top surface of the second via conductor is coplanar with the second portion of the top surface of the second via conductor;
and
wherein a second portion of the bottommost surface of the second conductive component interfaces the fifth dielectric material,
wherein the first and second conductive components are in next adjacent interconnect layers, and
wherein the first conductive component and the second conductive component are offset such that the first portion of the bottommost surface of the second conductive component is not vertically aligned with the first portion of the topmost surface of the first conductive component.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/464,055Filed 4 May 2012
Published: US 2013/0292841 A17 Nov 2013
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/089
By forming openings in the dielectric parts: using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
H10W 20/435
Characterised by their conductive parts: cross-sectional shapes or dispositions of interconnections
H10W 20/47
Characterised by their insulating parts: comprising two or more dielectric layers having different properties, e.g. different dielectric constants