Packaged semiconductor die and CTE-engineering die pair
AssigneeIntel Corporation
InventorChuan Hu
Life of this patent
Estimating the term…
Abstract
Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.
Claims24
A semiconductor package, comprising:
- a bumpless build-up layer (BBUL) substrate comprising an encapsulant layer and a plurality of build-up layers;
- a semiconductor die embedded in the BBUL substrate and having a surface area;
- and
- a CTE-engineering die embedded in the BBUL substrate and bonded to the semiconductor die, and having a surface area the same and in alignment with the surface area of the semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.
A method of fabricating a semiconductor package, the method comprising:
- thinning a semiconductor wafer from a backside of the semiconductor wafer;
- and, subsequently, bonding, via the backside, the semiconductor wafer to a CTE-engineering wafer or panel;
- and, subsequently,
- singulating the semiconductor wafer and the CTE-engineering wafer or panel to form a plurality of semiconductor die and CTE-engineering die pairs;
- and, subsequently,
- packaging a semiconductor die and CTE-engineering die pair in a single package, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.
A semiconductor package, comprising:
- a bumpless build-up layer (BBUL) substrate having a land side, the BBUL substrate comprising an encapsulant layer and a plurality of build-up layers;
- a semiconductor die embedded in the (BBUL) substrate, the semiconductor die comprising an active side proximate to the land side of the (BBUL) substrate, and comprising a back side having a surface area distal from the land side of the (BBUL) substrate;
- and
- a CTE-engineering die embedded in the (BBUL) substrate and bonded to the semiconductor die, the CTE-engineering die having a surface area the same and in alignment with the surface area of the back side of the semiconductor die, wherein the CTE of the CTE-engineering die dominates a combined CTE of the semiconductor die and the CTE-engineering die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.
A semiconductor package, comprising:
- a substrate;
- a semiconductor die coupled to the substrate and having a surface area;
- and
- a CTE-engineering die bonded to the semiconductor die, and having a surface area the same and in alignment with the surface area of the semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.
Dependencies are inferred from the claim text.