US 10,096,524 B1Granted

Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors

AssigneeInternational Business Machines Corporation

InventorsZhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu

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Abstract

Methods are provided for fabricating semiconductor fins having uniform profiles. For example, a method includes forming semiconductor fins on a substrate, including a first semiconductor fin disposed in a first device region, and a second semiconductor fin disposed in a second device region. The first and second semiconductor fins are formed of different types of semiconductor material, and are initially formed to have different widths and heights. A semiconductor fin trimming process is performed, which is selective to the semiconductor material of the second semiconductor fin, so that the fin trimming process results in the formation of semiconductor fins having substantially equal heights and equal widths across the device regions as a result of the fin trimming process. The semiconductor fins in different device regions are initially formed with non-uniform profiles (e.g., differential heights and widths) to compensate for micro-loading and etch rate variations during the fin trimming process.

Claims19

Dependent claims

A method for fabricating a semiconductor device, comprising:

forming a plurality of semiconductor fins on a substrate, wherein the plurality of semiconductor fins comprises a first semiconductor fin disposed in a first device region, and a second semiconductor fin disposed in a second device region, wherein the first and second semiconductor fins are formed of different types of semiconductor material, wherein the first semiconductor fin and the second semiconductor fin are formed to have different widths and heights;
and
performing a semiconductor fin trimming process, which is selective to the semiconductor material of the second semiconductor fin, to trim the first and second semiconductor fins to have substantially a same width and substantially a same height,
wherein performing the semiconductor fin trimming process comprises performing a cyclic etch process to incrementally etch the first and second semiconductor fins, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle, wherein the etch cycle comprises:
performing an etch process to partially etch the first and second semiconductor fins using an etch chemistry and environment which is configured to etch the semiconductor material of the second semiconductor fin selective to the semiconductor material of the first semiconductor fin;
and
performing a thermal treatment to remove by-products of the etch process.

4 more elements

A method for fabricating a semiconductor device, comprising:

patterning a layer of first epitaxial semiconductor material, which is disposed on a semiconductor substrate, to form a trench opening in the layer of first epitaxial semiconductor layer down to the semiconductor substrate, wherein the trench opening is formed in a first device region;
forming a first semiconductor fin in the trench opening, wherein the first semiconductor fin is formed of a second epitaxial semiconductor material which is different from the first epitaxial semiconductor material, wherein the first semiconductor fin is epitaxially grown in the trench opening using a bottom-up epitaxial growth process to partially fill the trench opening with the second epitaxial semiconductor material to a height of H1 which is less than a thickness T of the layer of first epitaxial semiconductor material, wherein a width of the trench opening defines a width W1 of the first semiconductor fin;
etching the layer of first epitaxial semiconductor material to form a second semiconductor fin in a second device region which comprises the first epitaxial semiconductor material, and to remove remaining portions of the layer of first epitaxial semiconductor material in the first and second device regions, wherein the second semiconductor fin is formed to have a width W2 which is greater than W1, and wherein a height H2 of the second semiconductor fin is defined by the thickness T of the layer of first epitaxial semiconductor material;
and
performing a semiconductor fin trimming process, which is selective to the first epitaxial semiconductor material of the second semiconductor fin, to trim the first and second semiconductor fins to have substantially a same width W3 and substantially a same height H3, wherein W3 is less than W2 and W1, and wherein H3 is less than H2 and H1.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/786,744Filed 18 Oct 2017
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0245
Of fin field-effect transistors [FinFET]: by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/0188
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their isolation regions