Dummy MOL removal for performance enhancement

A method of forming an integrated chip, comprising:

• forming a plurality of gate structures over a semiconductor substrate;
• forming a well region comprising a plurality of source/drain regions, wherein the well region underlies the plurality of gate structures;
• forming an original middle-of-the-line (MOL) layer having a plurality of MOL structures vertically disposed between the semiconductor substrate and a plane extending along upper surfaces of the plurality of gate structures and laterally interleaved between the plurality of gate structures, wherein the plurality of MOL structures respectively comprise a continuous conductive structure;
• removing a part but not all of a single one of the plurality of MOL structures continuously extending over the well region to form a modified MOL layer, wherein removing the part of the single one of the plurality of MOL structures forms two separate MOL segments from the single one of the plurality of MOL structures;
• and
• forming a dielectric material within a location from which the part of the single one of the plurality of MOL structures was removed, wherein the dielectric material separates the two separate MOL segments along a first direction and continuously extends between sidewalls of the plurality of gate structures along a second direction perpendicular to the first direction.

A method of forming an integrated chip, comprising:

• forming a plurality of gate structures over a semiconductor substrate;
• forming a plurality of source/drain regions between the plurality of gate structures;
• forming an original middle-of-the-line (MOL) layer having a plurality of MOL structures vertically disposed between the semiconductor substrate and a plane extending along upper surfaces of the plurality of gate structures and laterally interleaved between the plurality of gate structures, wherein the original MOL layer comprises MOL active structures that are configured to be subsequently connected to an overlying conductive interconnect and MOL dummy structures that are not configured to be subsequently connected to any overlying conductive interconnect;
• and
• removing a part but not all of the MOL active structures to form a modified MOL layer;
• and
• forming an inter-level dielectric (ILD) layer to completely fill a location from which the part of the original MOL layer was removed.