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US 10,096,520 B2Granted
Semiconductor device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSanghoon Baek, Jae-Ho Park, Seolun Yang, Taejoong Song, Sang-Kyu Oh
Life of this patent
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Abstract
A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.
Claims20
A semiconductor device comprising:
- a substrate including a first region, a second region and a third region that is disposed between the first region and the second region;
- a plurality of first active patterns protruding upward from the first region of the substrate, each of the first active patterns extending lengthwise in a first direction crossing the first to third regions, and the first active patterns being spaced apart from one another in a second direction crossing the first direction;
- a plurality of second active patterns protruding upward from the second region of the substrate, each of the second active patterns extending lengthwise in the first direction, and the second active patterns being spaced apart from one another in the second direction;
- a first gate structure disposed on the first region of the substrate and crossing the plurality of first active patterns;
- and
- a second gate structure disposed on the second region of the substrate and crossing the plurality of second active patterns,
- wherein a device isolation layer is disposed on the third region of the substrate,
- the plurality of first active patterns has a different pitch from the plurality of second active patterns,
- a width of each of the plurality of first active patterns is substantially the same as a width of each of the plurality of second active patterns, and
- the first region is a static random access memory (SRAM) region and the second region is a peripheral circuit region.
7 more elements
A semiconductor device comprising:
- a substrate including a first region, a second region and a third region that is disposed between the first region and the second region, first, second and third trenches being defined in the first, second and third regions of the substrate, respectively;
- a plurality of first active patterns protruding upward from the first region of the substrate, each of the first active patterns extending lengthwise in a first direction crossing the first to third regions, and the first active patterns being spaced apart from one another in a second direction crossing the first direction;
- a plurality of second active patterns protruding upward from the second region of the substrate, each of the second active patterns extending lengthwise in the first direction, and the second active patterns being spaced apart from one another in the second direction;
- a device isolation layer filling the first, second and third trenches in the first, second and third regions of the substrate;
- a first gate structure disposed on the first region of the substrate and crossing the plurality of first active patterns;
- and
- a second gate structure disposed on the second region of the substrate and crossing the plurality of second active patterns,
- wherein the first trench is defined between two of the first active patterns,
- the second trench is defined between two of the second active patterns,
- the third trench in the third region of the substrate is situated between the first and second regions, and
- a bottom of the third trench is lower than bottoms of the first and second trenches.
8 more elements
A semiconductor device comprising:
- a substrate including a first region, a second region and a third region that is disposed between the first region and the second region;
- a device isolation layer disposed on the first, second and third regions of the substrate;
- a plurality of first active patterns on the first region of the substrate, each of the first active patterns having an upper portion vertically protruding beyond a top surface of the device isolation layer, each of the first active patterns extending lengthwise in a first direction crossing the first to third regions, and the first active patterns being spaced apart from one another in a second direction crossing the first direction;
- a plurality of second active patterns on the second region of the substrate, each of the second active patterns having an upper portion vertically protruding beyond the top surface of the device isolation layer, each of the second active patterns extending lengthwise in the first direction, and the second active patterns being spaced apart from one another in the second direction;
- a first gate covering opposite sidewalls and a top surface of the upper portion of each of the first active patterns;
- and
- a second gate structure covering opposite side surfaces and a top surface of the upper portion of each of the second active patterns,
- wherein
- dummy patterns on the third region of the substrate.
6 more elements
Dependencies are inferred from the claim text.