Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method used during fabrication of a semiconductor device, the method comprising:

• forming a pair of sacrificial pedestals on a layer to be etched;
• forming a spacer layer over at least the pair of sacrificial pedestals;
• removing the pair of sacrificial pedestals and a portion of the spacer layer to form pairs of sacrificial spacers;
• filling the space previously occupied by the sacrificial pedestals with spacer material, the spacer material extending to the walls of the sacrificial spacers and the layer to be etched between the sacrificial spacers;
• planarizing the sacrificial spacers and the spacer material;
• and
• removing the sacrificial spacers.

A method used during fabrication of a semiconductor device, the method comprising:

• forming a pair of sacrificial pedestals on a layer to be etched;
• forming a spacer layer over at least the pair of sacrificial pedestals;
• removing the pair of sacrificial pedestals and a portion of the spacer layer to form pairs of sacrificial spacers;
• filling the space previously occupied by the sacrificial pedestals with spacer material, the spacer material extending to the walls of the sacrificial spacers and the layer to be etched between the sacrificial spacers;
• planarizing the sacrificial spacers and the spacer material;
• removing the sacrificial spacers;
• and
• etching the layer to be etched, the etching removing at least a portion of the spacer material.