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US 10,096,379 B2Granted
Memory device and method for testing reliability of memory device
AssigneeMegaChips Corporation
InventorTakahiko Sugahara
Life of this patent
Estimating the term…
Abstract
A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.
Claims11
A memory device comprising:
- memory array circuitry that stores content data;
- random number generator circuitry that generates a true random number;
- and
- memory controller circuitry connected to the memory array circuitry and the random number generator circuitry, wherein the memory controller circuitry:
- performs a reliability test only on the memory array circuitry out of the memory array circuitry and the random number generator circuitry on receipt of a first test command from an external device, and
- performs a reliability test only on the random number generator circuitry out of the memory array circuitry and the random number generator circuitry on receipt of a second test command from the external device, wherein
- the memory controller circuitry includes a self-test circuit that performs the reliability test of the random number generator circuitry, and
- the self-test circuit (i) starts checking irreproducibility of random number values, which are generated by the random number generator circuitry, on receipt of input of count information for specifying a number of counts to cause the random number generator circuitry to generate the random number values, and (ii) sends a check result to the external device on completion of checking.
5 more elements
A method for testing reliability of a memory device,
- the memory device including memory array circuitry that stores content data, random number generator circuitry that generates a true random number, and memory controller circuitry that connects to the memory array circuitry, the method comprising:
- performing, by the memory controller circuitry, a reliability test only on the memory array circuitry out of the memory array circuitry and the random number generator circuitry on receipt of a first test command from an external device;
- and
- performing, by the memory controller circuitry, a reliability test only on the random number generator circuitry out of the memory array circuitry and the random number generator circuitry on receipt of a second test command from the external device, wherein
- the memory controller circuitry includes a self-test circuit that performs the reliability test of the random number generator circuitry, and
- the self-test circuit (i) starts checking irreproducibility of random number values, which are generated by the random number generator circuitry, on receipt of input of count information for specifying a number of counts to cause the random number generator circuitry to generate the random number values, and (ii) sends a check result to the external device on completion of checking.
3 more elements
Dependencies are inferred from the claim text.