US 10,096,378 B1Granted

On-chip capacitance measurement for memory characterization vehicle

AssigneePDF Solutions, Inc.

InventorsYih-Yuh Doong, Chao-Hsiung Lin, Sheng-Che Lin, Shihpin Kuo, Tzupin Shen, Chia-Chi Lin, Kimon Michaels

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Abstract

A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.

Claims22

Dependent claims

A method for designing a parametric test vehicle for bit-line capacitance measurement utilizing a layout of a memory chip comprising a plurality of bit-lines addressing a plurality of memory bit-cells in a memory block, the method comprising:

importing a layout of the memory chip;
selecting a first pair of transistors, comprising a first PMOS transistor and a first NMOS transistor, from the layout of the memory chip;
removing existing routing interconnect for the selected first PMOS transistor and the first NMOS transistor;
creating customized interconnect layers (CIL) to connect the first PMOS transistor to one end of a bit-line at one side of the memory block, and, to connect the first NMOS transistor to the same end or a different end of the same bit-line;
driving the PMOS transistor with a first clock signal, and driving the NMOS transistor with a second clock signal, wherein the first clock signal and the second clock signal are synchronized but non-overlapping;
measuring current flowing through the bit-line to calculate a capacitance of the bit-line;
and
incorporating the selected PMOS and NMOS transistors with the CIL into the layout of the memory chip to create a modified memory chip layout, such that a wafer fabricated using the modified memory chip layout comprises a memory chip with a built-in test vehicle for capacitance measurement.

5 more elements

Dependencies are inferred from the claim text.