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US 10,096,372 B2Granted
Shift register and display apparatus
AssigneesHannStar Display (Nanjing) Corporation, Hannstar Display Corp.
InventorChien-Ting Chan
Life of this patent
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Abstract
A shift register and a display apparatus are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives a pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The duty cycle of the clock signal is less than 50 percent.
Claims16
A shift register, comprising:
- a pre-charge unit configured to receive a first input signal and a second input signal and to output a pre-charge signal via a first node based on the first input signal and the second input signal, wherein the pre-charge unit comprises:
- a first transistor, wherein a gate of the first transistor is configured to receive a scan signal outputted by a previous four stage shift register, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal;
- and
- a second transistor, wherein a gate of the second transistor is configured to receive a scan signal outputted by a next four stage shift register, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor;
- a pull-up unit coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and to output a scan signal via a second node based on the pre-charge signal and the clock signal;
- a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and to control whether to pull down the scan signal to a first reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
- and
- a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and to control whether to keep the scan signal at the first reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
- wherein a duty cycle of the clock signal is less than 50 percent.
6 more elements
A display apparatus, comprising:
- a display panel;
- and
- a gate driver configured to drive the display apparatus and having 1st-Nth stage shift registers, wherein the ith stage shift register of the 1st-Nth stage shift registers comprises:
- a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal, wherein the pre-charge unit of the ith stage shift register comprises:
- a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal;
- and
- a second transistor, wherein a gate of the second transistor is configured to receive a second input signal, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor, wherein:
- when i is from 1 to 4, the first input signal is a starting signal, and the second input signal is an (i+4)th stage scan signal outputted by the (i+4)th stage shift register of the 1st-Nth stage shift registers;
- when i is from (N−3) to N, the first input signal is an (i−4)th stage scan signal outputted by the (i−4)th stage shift register of the 1st-Nth stage shift registers, and the second input signal is an ending signal;
- when i is from 5 to (N−4), the first input signal is an (i−4)th stage scan signal outputted by the (i−4)th stage shift register of the 1st-Nth stage shift registers, and the second input signal is an (i+4)th stage scan signal outputted by the (i+4)th stage shift register of the 1st-Nth stage shift registers;
- a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and output an ith stage scan signal via a second node based on the pre-charge signal and the clock signal;
- a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the ith stage scan signal to a first reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
- and
- a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the ith stage scan signal at the first reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
- wherein a duty cycle of the clock signal is less than 50 percent.
12 more elements
Dependencies are inferred from the claim text.