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AssigneeToshiba Memory Corporation
InventorsTakayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
Estimating the term…
A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
A memory system comprising:
Dependencies are inferred from the claim text.
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Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
About 9 years 6 months of term left · ends 13 Apr 2036 (estimated)
Embodiments described herein relate generally to a memory system.
A memory system including a NAND flash memory and a controller which controls such a memory is known.
FIG. 1 illustrates functional blocks of a memory system of a first embodiment;
FIG. 2 illustrates functional blocks of a memory device of the first embodiment;
FIG. 3 illustrates an example of components and connections of a block of the memory device of the first embodiment;
In general, according to one embodiment, a memory system includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
Embodiments will now be described with reference to the figures. In the following description, components with substantially the same functionalities and configurations will be referred to with the same reference numerals, and repeated descriptions may be omitted. The entire description for a particular embodiment also applies to another embodiment unless it is explicitly mentioned otherwise or obviously eliminated. Each functional block can be implemented as hardware, computer software, or combination of the both. It is not necessary that functional blocks are distinguished as in the following examples. For example, some of the functions may be implemented by functional blocks different from those illustrated below. Furthermore, an illustrated functional block may be divided into functional sub-blocks.
Any step in a flow of a method of an embodiment is not limited to any illustrated order, and can occur in an order different from an illustrated order and/or can occur concurrently with another step.