Erasable block segmentation for memory
AssigneeMicron Technology, Inc.
InventorRamin Ghodsi
Life of this patent
Estimating the term…
Abstract
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.
Claims18
An apparatus, comprising a block of memory having segmented portions forming sub-blocks, and wherein multiple sub-blocks are coupled electrically to one another through at least one common data line, each of the sub-blocks corresponding to a respective segmented source, wherein each segmented source is electrically isolated from the other segmented sources of the block of memory, wherein the apparatus is configured to apply a first bias voltage to a respective one of the segmented sources of a sub-block selected to be erased during an erase operation, and to apply a second bias voltage to another of the number of segmented sources of a sub-block of the block of memory not selected to be erased during the erase operation, the first bias voltage being greater than the second bias voltage, and wherein a bias voltage that the apparatus is configured to apply to drain select lines coupled to the drain select devices of non-selected ones of the sub-blocks is no more than 75% of the first bias voltage.
An apparatus, comprising:
- a block of memory having two or more segmented portions, each portion forming a separate sub-block of the block of memory;
- multiple memory cell strings in each of the sub-blocks in the block of memory, the multiple memory cell strings being couplable by a common source select line, the multiple memory cell strings within one sub-block being configured to be erasable independently of the multiple memory cell strings in another sub-block;
- a source select device and a drain select device coupled to a respective one of each of the multiple memory cell strings, wherein the source select device on each of the multiple memory cell strings has a higher breakdown voltage than the drain select device on the respective string;
- and
- a first segmented source coupled to the multiple memory cell strings of the first sub-block, and a second segmented source coupled to the memory cell strings of the second sub-block, the first segmented source being electrically isolated from the second segmented source.
An apparatus, comprising:
- a block of memory having segmented portions forming sub-blocks, the sub-blocks being coupled electrically to one another through a common source select line, each of the sub-blocks corresponding to a respective one of a number of segmented sources that are electrically isolated from other segmented sources of the block of memory memory;
- at least one string of memory cells in each of the sub-blocks;
- and
- a drain select device coupled to respective ones of each of the memory cell strings, each of the drain select devices being configured to be activated by a separate drain select line, wherein each of the drain select devices has an asymmetric dopant profile.
Dependencies are inferred from the claim text.