US 10,096,362 B1 · Switching block configuration bit comprising a non-volatile memory cell

Abstract

A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.

Claims20

Dependent claims

A circuit, comprising:

a non-volatile switch comprising an input node, an output node and a control gate, the input node connected to a first conductive line of a switching block routing array and the output node connected to a second conductive line of the switching block routing array;
a volatile switch having a first contact and a second contact, the second contact is conductively connected to the control gate of the non-volatile switch;
and
a program circuit configured to selectively provide a voltage from a voltage source to the first contact of the volatile switch.

1 more element

A configuration bit for a node of a switching block routing array, comprising:

a transistor element having a control gate, a first terminal coupled to an input node of the switching block routing array and a second terminal coupled to an output node of the switching block routing array;
a two-terminal volatile resistive switching device, having a second electrode connected to the control gate and a first electrode;
and
a programming input provided to the first electrode of the two-terminal volatile resistive switching device, wherein:
the programming input supplies a signal to the two-terminal volatile resistive switching device via the first electrode,
the two-terminal volatile resistive switching device has a high resistance state in response to a magnitude of the signal being zero or about zero,
the two-terminal volatile resistive switching device transitions to a low resistance state in response to the magnitude increasing to a non-zero threshold voltage, and
the two-terminal volatile resistive switching device transitions from the low electrical resistance to the high electrical resistance in response to the magnitude decreasing below the non-zero threshold voltage, or below a second non-zero threshold voltage.

5 more elements

Dependencies are inferred from the claim text.

Switching block configuration bit comprising a non-volatile memory cell

Life of this patent

Switching block configuration bit comprising a non-volatile memory cell

Life of this patent

Abstract

Claims20