Distributed cascode current source for RRAM set current limitation

An apparatus, comprising:

• a memory element of a memory cell of a memory cell array, wherein the memory element is coupled to a source line of the memory cell array through a word line select transistor;
• a current limiting device coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cell, wherein the current limiting device comprises a pull-down transistor biased in saturation;
• and
• an array control circuitry coupled to the memory cell array, wherein the array control circuitry comprises a diode configured stack of transistors, wherein a first transistor of the stack is selectably coupled to a gate of the word line select transistor and a second transistor of the stack is coupled to a gate of the pull-down transistor.

A method, comprising:

• selecting at least one memory cell of a memory array;
• biasing a gate of a cell select transistor of the at least one memory cell into saturation via a word line corresponding to the at least one memory cell;
• and
• biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation;
• wherein biasing the gate of the cell select transistor comprises biasing the gate of the cell select transistor more than a threshold voltage above the gate of the pull-down transistor.