Dynamic management of programming states to improve endurance
AssigneeSanDisk Technologies LLC
InventorsNian Niles Yang, Abhijeet Manohar
Life of this patent
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Abstract
A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.
Claims19
A storage device comprising:
- a memory comprising memory blocks that have circuitry for at least three bits per cell in the memory blocks and that use a default programming mode for the at least three bits per cell;
- a controller coupled with the memory that is configured to receive a programming request for the memory blocks;
- and
- program state circuitry that operates with the default programming mode using programming for the at least three bits per cell or operates with a modified programming mode using single level cell (SLC) programming, wherein the modified programming mode with SLC includes first programming at least some of the memory blocks that have circuitry for at least three bits per cell using the SLC programming with a program verify level corresponding to SLC and second programming using the SLC programming with a modified program verify level corresponding with two bits per cell rather than the at least three bits per cell.
A storage device comprising:
- a means for programming a memory with at least three bits per cell memory blocks using a default programming mode for the at least three bits per cell;
- a means for receiving a programming request for the at least three bits per cell memory blocks;
- a means for programming the at least three bits per cell memory blocks with the default programming mode using three bits per cell programming;
- and
- a means for programming the at least three bits per cell memory blocks with a modified programming mode using single level cell (SLC) programming, wherein the modified programming mode with SLC includes first programming the at least three bits per cell memory blocks using single level cell (SLC) programming with a program verify level corresponding to SLC, and includes
- second programming the at least three bits per cell memory blocks using the SLC programming with a modified program verify level corresponding with a fewer bits per cell than the at least three bits per cell.
Dependencies are inferred from the claim text.