SRAM with error correction in retention mode
AssigneeAmbiq Micro, Inc.
InventorsChristophe J. Chevallier, Stephen James Sheafor
Life of this patent
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Abstract
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
Claims12
A method of operating an SRAM circuit comprising the sequential steps of:
- writing information in SRAM bit cell arrays;
- lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit;
- raising the voltage supplied to the SRAM bit cell arrays, and
- reading and correcting information stored in the SRAM bit cell arrays using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays, with the ECC block acting to repair stored information.
A method of handling information in one or more SRAM array blocks, comprising the steps of:
- testing the SRAM array blocks to determine lowest retention voltage at which, for a given first number of bits, no more than a second number of bits fail,
- storing the value of this lowest retention voltage;
- generating related ECC code based on a set of data and using an error correcting code (ECC) block connected to at least some of the SRAM arrays;
- writing the set of data and its related ECC code to the SRAM array,
- lowering the SRAM array voltage to a voltage equal to the lowest retention voltage,
- raising the SRAM array voltage to an operation voltage,
- reading some of the set of data and related ECC code of the SRAM array;
- and
- repairing some of the set of data of the SRAM array using the related ECC code.
A method of determining lowest usable set retention voltage in one or more SRAM array blocks, comprising the steps of:
- setting a retention voltage,
- writing a data pattern in the SRAM array blocks;
- lowering the SRAM array voltage to the set retention voltage;
- raising the SRAM array voltage to an operational voltage;
- reading data and comparing the read data to the data pattern;
- and
- decrementing the set retention voltage if no more than a predetermined set of bits fail in the read data pattern.
Dependencies are inferred from the claim text.