System and memory controller for interruptible memory refresh

A system for refreshing one or more DRAM modules, the system comprising:

• a memory controller, the memory controller configured to:
• communicate a refresh command, in response to a refresh timer, to a DRAM;
• and
• communicate a first command to the DRAM after execution of a first segment refresh has begun and before execution of a second segment refresh has begun;
• and
• the DRAM configured to:
• initiate an interruptible refresh in response to the communicated refresh command, the interruptible refresh comprising execution of a plurality of segment refreshes, the execution of the plurality of segment refreshes separated by interrupt boundaries, the plurality of segment refreshes comprising the first segment refresh and the second segment refresh, the first segment refresh and the second segment refresh separated by a first interrupt boundary;
• execute the first command at the first interrupt boundary after execution of the first segment refresh;
• delay execution of the second segment refresh until after the first command has been executed;
• and
• complete the interruptible refresh without additional refresh commands from the memory controller.

A method for refreshing one or more modules of DRAM, the modules communicatively coupled to one or more memory controllers, the method comprising:

• detecting, by a first memory controller, that a DRAM requires a refresh of two or more stored values within the DRAM;
• sending, by the first memory controller and based on the detecting, a first command to the DRAM, the first command causing the DRAM to start refresh of the two or more stored values;
• sending, by the first memory controller during execution of the refresh command and before completion of the refresh but after start of the refresh by the DRAM, a second command to the DRAM, the second command causing the DRAM to delay refresh of the two or more stored values, the second command causing the DRAM to retrieve information from the two or more stored values;
• and
• receiving, by the first memory controller during execution of the refresh command and before completion of the refresh but after start of the refresh by the DRAM, a response to the second command, the response including the retrieved information from the DRAM.